EP80579 Datasheet, PDF (1244/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.6 Offset 06h: PCISTS – Device Status Register
Table 35-11. Offset 06h: PCISTS: PCI Device Status Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: 06h
Offset End: 07h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: 06h
Offset End: 07h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 10h
Power Well: Core
Bit Range
15
14
13
12
11
10 : 09
08
07
06
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
DPE
SSE
RMA
RTA
STA
DST
MDPE
FB2B
Reserved
MC66
CL
IS
Reserved
Detected Parity Error: The device does not implement this
functionality. The bit is hardwired to 0. The EP80579 uses
signals for errors.
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
DEVSEL Timing
Master Data Parity Error: The device does not implement
this functionality. The bit is hardwired to 0. The EP80579
uses signals for errors.
Fast Back-to-Back Capable
Reserved
66 MHz Capable
Capabilities List
Interrupt Status
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
00b
0h
0h
0h
0h
1
0h
0h
Bit Access
RO
RO
RO
RO
RO
RO
RO
RO
RV
RO
RO
RO
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1244
August 2009
Order Number: 320066-003US