EP80579 Datasheet, PDF (730/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Warning:
Note:
Warning:
Note:
Warning:
Note:
A system that has locked up and can not be restarted with power button press is
probably very broken (bad power supply, short circuit on some bus, etc.) and beyond
the CMI’s recovery mechanisms.
8. After step 3 (third timeout), if a reset is attempted (using a button that pulses
PWROK low or via the message on the SMBus Slave Interface), the CMI attempts to
reset the system.
9. If step 8 (reset attempt) is successful, then the BIOS is run. The CMI continues
sending messages until the BIOS clears the SECOND_TO_STS bit.
It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the
LAN device driver from working properly. The alerts reset part of the LAN and would
prevent an operating system’s device driver from sending or receiving some messages.
10. If step 8 (reset attempt), is unsuccessful, then the CMI continues sending
messages. The CMI does not attempt to reboot the system again without external
intervention.
A system that has locked up and can not be restarted with the power button press is
broken (bad power supply, short circuit on some bus, etc.)
11. This and the following rules/steps apply if the user intervention (power button
press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog
timer.
12. After step 1 (second timeout), if the user does a Power Button Override, the system
goes to an S5 state. The CMI continues sending messages at this point.
13. After step 12 (power button override), if the user presses the power button again,
the system must wake to an S0 state and the CPU must start executing the BIOS.
14. If step 13 (power button press) is successful in waking the system, the CMI
continues sending messages until the BIOS clears the SECOND_TO_STS bit.
It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the
LAN device driver from working properly. The alerts reset part of the LAN and would
prevent an operating system’s device driver from sending or receiving some messages.
15. If step 13 (power button press) is unsuccessful in waking the system, the CMI
continues sending messages. The CMI does not attempt to reboot the system again
until some external intervention occurs (reset, power failure, etc.).
A system that has locked up and can not be restarted with power button press is
broken (bad power supply, short circuit on some bus, etc.) and beyond the CMI’s
recovery mechanisms.
16. After step 1 (second timeout), if a reset is attempted (using a button that pulses
PWROK low or via the message on the SMBus Slave Interface), the CMI attempts to
reset the system.
17. If step 16 (reset attempt) is successful, then the BIOS is run. The CMI continues
sending messages until the BIOS clears the SECOND_TO_STS bit.
It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the
LAN device driver from working properly. The alerts reset part of the LAN and would
prevent an operating system’s device driver from sending or receiving some messages.
18. If step 16 (reset attempt), is unsuccessful, then the CMI continues sending
messages. The CMI does not attempt to reboot the system again without external
intervention.
A system that has locked up and can not be restarted with power button press is
broken (bad power supply, short circuit on some bus, etc.)
Intel^® EP80579 Integrated Processor Product Line Datasheet
730
August 2009
Order Number: 320066-003US