EP80579 Datasheet, PDF (747/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.3.9 Offset 6Bh: PHRC: PIRQH Routing Control Register
Table 19-22. Offset 6Bh: PHRC: PIRQH Routing Control Register
Description: PHRC - Routing Control Register
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 6Bh
Offset End: 6Bh
Size: 8 bit
Default: 80h
Power Well: Core
Bit Range
07
06 :04
03 :00
Bit Acronym
Bit Description
Sticky
REN
Reserved
IR
Interrupt Routing Enable:
0 = The corresponding PIRQ is routed to one of the legacy
interrupts specified in bits[03:00].
1 = The PIRQ is not routed to the 8259.
Note:
Reserved
IRQ Routing:
Bits Mapping
0000 Reserved
0001 Reserved
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
Bits
1000
1001
1010
1011
1100
1101
1110
1111
Mapping
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
Bit Reset
Value
1
000h
0h
Bit Access
RW
RW
19.2.4
19.2.4.1
LPC I/O Configuration Registers
Offset 80h: iOD: i/O Decode Ranges Register
Table 19-23. Offset 80h: IOD: I/O Decode Ranges Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 80h
Offset End: 81h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :13
12
11 :10
Bit Acronym
Bit Description
Sticky
Reserved
FDD
Reserved
Reserved.
FDD Range: This field determines which range to decode
for the FDD Port
0 = 3F0 – 3F5h, 3F7h (Primary)
1 = 370 – 375h, 377h (Secondary)
Reserved
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
747