EP80579 Datasheet, PDF (1031/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
26.10.2
26.10.3
3. When system software determines that it should pause the EHC schedule, one or
both of the Schedule Enable bits are written to 0. When this happens, the EHC
responds as follows:
a. The schedule disables are handled independently. In other words, the
asynchronous and periodic disables may take effect in any order and vary
greatly in latency.
b. If the Periodic Schedule Enable is cleared, up to two more periodic transactions
may be seen on the USB ports. Reads associated with the periodic schedule
cease when the first fetch for a new transaction would normally be initiated;
any reads required to execute an already partially-fetched transaction will
continue to be generated. Writes associated with the periodic schedule may
continue until all pending transactions in the periodic DMA engine’s transaction
queue are completed. The Periodic Schedule Status bit is cleared when the
memory reads have completed and the memory writes have been internally
posted.
Multiple high-bandwidth packets are considered one transaction.
c. If the Asynchronous Schedule Enable is cleared, up to two more asynchronous
transactions may be seen on the USB ports. Reads associated with the
asynchronous schedule cease when the first fetch for a new transaction would
normally be initiated; any reads required to execute an already partially-
fetched transaction will continue to be generated. Writes associated with the
asynchronous schedule will continue until all pending transactions in the
asynchronous DMA engine’s transaction queue are completed. The
Asynchronous Schedule Status bit is cleared when the memory reads have
completed and the memory writes have been internally posted.
4. Before setting a Schedule Enable bit, software reads the USB 2.0 Status register to
make sure that the corresponding Schedule Status bit is cleared.
5. When system software determines that it should reenable the EHC, one or both of
the Schedule Enable are written to 1. When this happens, the EHC responds as
described in the initial start-up case above.
The CMI does not implement a similar pause mechanism in the classic host controllers,
which conflicts with the recommendation in the EHCI Specification.
Suspend Feature
The EHCI Specification describes the details of Port Suspend and Resume.
ACPI Device States
The USB 2.0 function only supports the D0 and D3 PCI Power Management states.
Notes regarding implementation of the Device States:
1. The EHC hardware does not inherently consume any more power when it is in the
D0 state than it does in the D3 state. However, software is required to suspend or
disable all ports prior to entering the D3 state such that the maximum power
consumption is reduced.
2. In the D0 state, all implemented EHC features are enabled.
3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.
Since the Debug Port uses the same memory range, the Debug Port is only
operational when the EHC is in the D0 state.
4. In the D3 state, the EHC interrupt must never assert for any reason. The internal
PME# signal is used to signal wake events, etc.
5. When the Device PowerState field is written to D0 from D3, an internal reset is
generated. See Section 26.4.3 for general rules on the effects of this reset.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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