EP80579 Datasheet, PDF (1338/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
36.2.6
36.3
Additionally, one of the GbE controllers (GbE0) is located in the auxiliary power well.
This allows monitoring of LAN traffic on this interface while the rest of the EP80579 is in
ultra-low-power mode. The details of power well manipulation is outside the scope of
this chapter and the reader is referred to Chapter 37.0, “Gigabit Ethernet Controller”
for details.
Serial EEPROM Interface
A single four-wire Microwire* interface is provided for connection of an optional,
externally connected serial EEPROM. The serial EEPROM may be used to provide
configuration information to the GbE controllers upon power-up or reset. All three
controllers share the same EEPROM. A fixed priority arbiter controls access to the
EEPROM where highest priority is given to GbE 0 then GbE 1 and finally GbE 2.
Software may also access this EEPROM. It can either use the controller built in to the
MAC to read the EEPROM, or access the EEPROM directly using the EEPROM's 4-wire
interface via registers also provided in the MAC.
Local Expansion Bus Interface (LEB)
The Local Expansion Bus Controller (LEB) provides a low-speed interface to external
expansion target devices.
The Expansion Bus Controller includes a 25-bit address bus and a 16-bit-wide data
path. The Expansion Bus controller maps transfers between the EP80579 and external
devices. The Expansion Bus supports these target devices:
• Intel multiplexed
• Intel non-multiplexed
• Intel StrataFlash^® technology
• Intel StrataFlash^® Synchronous Memory
• Micron* Flow-Through ZBT
• Motorola* multiplexed
• Motorola* non-multiplexed
• Texas Instruments* Host Port Interface* (HPI)
Applications having less than 16-bit, external target devices may connect to an 8-bit
interface. For TI DSPs that support an internal bus width of 32 bits, the multiplexed
HPI-8 or HPI-16 interface can be used to complete these transfers.
The Expansion Bus Controller features include:
• Outbound transfers — the EP80579 is the master to an external target device.
• Eight programmable target chip selects.
• Twenty-five bits of address; 16 bits of data.
• Supports Intel-mode and Motorola-mode bus cycles.
• Supports Intel StrataFlash.
• Supports 66-MHz Synchronous Intel StrataFlash Memory (16-bit only).
• Supports 16-bit Micron* Flow-Through ZBT (Zero bus turnaround) SRAMS.
• Supports 8-bit and 16-bit Texas Instruments* HPI specifications.
• Multiplexed or non-multiplexed address/data buses for Intel/Motorola/HPI bus
cycles.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1338
August 2009
Order Number: 320066-003US