EP80579 Datasheet, PDF (483/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-90. Offset 80h: DRAM_FERR - DRAM First Error Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 80h
Offset End: 81h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :08
07
06
05 :04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
MTCA
Memory Test Complete: Not an error condition. This bit
is set by hardware to signal BIOS that hardware testing of
the channel is complete. This bit is sticky through reset.
System software clears this bit by writing a 1 to the
Y
location.
1 = Hardware-based test of DRAM is complete.
(NON-FATAL)
UERRA
Uncorrectable Error on Write: (Uncorrectable) This bit
is set on a detected error regardless of ECC mode, even if
ECC is disabled. However if the error was injected via
ECCDIAG, this bit is not set.
Note that the state of the ECCDIAG.MEMPEN does not
impact the setting of this bit. For more details please see
Section 16.1.1.44, “Offset 84h: ECCDIAG – ECC Detection/
Correction Diagnostic Register”.
Y
This bit is sticky through reset. System software clears this
bit by writing a 1 to the location.
0 = No parity error detected on writes to DRAM.
1 = Parity error detected on write to DRAM.
(NON-FATAL)
Reserved Reserved
ETDA
Error Threshold Detect: This bit is sticky through reset.
System software clears this bit by writing a 1 to the
location. This bit can be set by either a SEC or DED event,
if the corresponding error counter is set.
Y
0 = No Error Threshold detected
1 = Error Threshold detected.
(NON-FATAL)
USDEA
Uncorrectable Scrubber Data Error: This bit is sticky
through reset. System software clears this bit by writing a
1 to the location.
0 = No Scrubber Error Detected
Y
1 = Scrubber Error Detected.
(NON-FATAL)
URMEA
Uncorrectable Read Memory Error: (Uncorrectable)
Applies to non-scrub demand (normal demand fetch)
reads. This bit is sticky through reset. System software
clears this bit by writing a 1 to the location.
0 = No Uncorrectable Non-Scrub Demand Read Memory
Y
Error
1 = Uncorrectable Non-Scrub Demand Read Memory Error.
(NON-FATAL)
CRMEA
Correctable read memory Error: (Correctable) SECs
(Single Bit Error Correction) detected by normal demand
requests or scrub/demand fetch (normal read to memory).
This bit is sticky through reset. System software clears this
bit by writing a 1 to the location.
Y
0 = No Correctable Read Memory Error.
1 = Correctable Read Memory Error.
(NON-FATAL)
Bit Reset
Value
00h
0b
0b
00b
0b
0b
0b
0b
Bit Access
RO
RWC
RWC
RO
RWC
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
483