EP80579 Datasheet, PDF (1467/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-44. IMS1: Interrupt 1 Mask Set/Read Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08D0h
Offset End: 08D3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08D0h
Offset End: 08D3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08D0h
Offset End: 08D3h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
02
Rsvd
Reserved. Must be written as ‘0’
01
TXQE
Sets the mask for Transmit Queue Empty
00
TXDW
Sets the mask for Transmit Descriptor Written Back
Sticky
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
37.6.3.9
IMC1 – Interrupt 1 Mask Clear Register
Software uses this register to disable an interrupt condition that was previously
enabled. Interrupts are presented to the bus interface only when the mask bit is set
and the interrupt condition is active. The status of the mask bit is reflected in the “IMS0
– Interrupt 0 Mask Set/Read Register” on page 1459, and the status of the cause bit is
reflected in the “ICR0 – Interrupt 0 Cause Read Register” on page 1454. Software
disables a given interrupt by writing a 1 to the corresponding bit in this register, a 0 is
ignored.
Table 37-45. IMC1: Interrupt 1 Mask Clear Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08D8h
Offset End: 08DBh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08D8h
Offset End: 08DBh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08D8h
Offset End: 08DBh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 29
28
27
26
25 : 24
Rsvd
Reserved
ERR_INTBUS Clears the mask for Internal Bus Error
ERR_STAT Clears the mask for Statistic Register ECC Error
ERR_MCFSPF Clears the mask for the Filter Memory Errors
Rsvd
Reserved
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RV
WO
WO
WO
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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