EP80579 Datasheet, PDF (1842/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-19. DDR2-800 Interface AC Characteristics
Symbol
Parameter
Min
Max
Unit
Figures
Notes
System Memory Clock Timings
t_CK
DDR_CK[5:0] Period
t_CH
DDR_CK[5:0] High Time
t_CL
DDR_CK[5:0] Low Time
tJIT
DDR_CK[5:0] Cycle to Cycle Jitter
2.5
ns
49-9
1.120
ns
49-11
1.120
ns
49-12
130
ps
6
tSKEW_CK-CK
Skew between any two system memory differential
clock pairs (DDR_CK[5:0]/DDR_CK[5:0]#)
-
0.06T_CK
ps
49-10
6
DDR_CK[x] to DDR_CK[y]#
(where x does not equal y)
0.25T_CK
ps
49-10
6
tSKEW_CK-
DQS
Skew between any system memory clock pair and
any system memory strobe
–0.25T_CK +0.25T_CK
ps
49-13
6
System Memory Command and Control Signal Timings
tCVB
tCVA
DDR_RAS#, DDR_CAS#, DDR_WE#, DDR_A[14:0],
DDR_BA[2:0], DDR_CS[1:0]# Valid Before
DDR_CK Rising Edge
DDR_RAS#, DDR_CAS#, DDR_WE#, DDR_A[14:0],
DDR_BA[2:0], DDR_CS[1:0]# Valid After DDR_CK
Rising Edge
0.819
0.819
ns
49-8
ns
49-8
System Memory Data and Strobe Signal Timings
tDVB
DDR_DQ[63:0], DDR_ECC[7:0], DDR_DM[8:0]
Valid Before the corresponding DDR_DQS and
DDR_DQS_L Crossing
0.372
ns
49-5
6
tDVA
DDR_DQ[63:0], DDR_ECC[7:0], DDR_DM[8:0]
Valid Before the corresponding DDR_DQS and
DDR_DQS_L Crossing
0.372
ns
49-5
6
tDOPW
DDR_DQ[63:0], DDR_ECC[7:0] Output Valid Pulse
Width
1.120
ns
-
3, 6
tSU_DQS
DDR_DQ and DDR_ECC Input Setup Time to DQS
Crossing
–0.292
ns
49-4
1, 2, 6
tHD_DQS
DDR_DQ and DDR_ECC Input Hold Time After DQS
Crossing
+0.956
ns
49-4
1, 6
tWPRE
DDR_DQS Write Preamble Duration
0.875
(nom)
ns
49-6
6
tWPST
DDR_DQS Write Postamble Duration
1.00
(nom)
ns
49-7
6
Notes:
1.
Data to Strobe read setup and Data from strobe read hold minimum requirements specified are determined with the DQS
Delay programmed for a 90 degree phase shift.
2.
Refer to Figure 49-5. Negative minimum setup time at the EP80579 pins is correct – the DQS crossing at the EP80579 pins
is expected to arrive before data becomes valid. Data is latched by a delayed copy of DQS (see Note 1), which nominally
centers the strobe within the data valid window. Refer to the DDR2 Specification for further details.
3.
TDOPW defines the minimum time a given data bit is guaranteed valid at the pin. Note that this is greater than the sum of
minimum TDVA and TDVB, since strobe-to-data alignment uncertainty subtracts from those times.
4.
AC timings are specified into a 25 ohm test load (for DQ and DQS) or 50 ohm test load (for other signals) terminated to
Vdd/2
5.
This specification applies for writes only; that is, when the IMCH is driving the strobes as well as the clocks. Refer to the
JEDEC specification for an explanation of strobe to clock timing for DDR2 reads.
6.
Guaranteed by design.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1842
August 2009
Order Number: 320066-003US