EP80579 Datasheet, PDF (353/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
13.4
Note:
13.5
IMCH Register Introduction
The IMCH contains two sets of software accessible registers, accessed via the IA-32
core I/O address space: control registers I/O mapped into the IA-32 core I/O space,
which control access to PCI configuration space, and internal configuration registers
residing within the IMCH, which are partitioned into multiple logical device register sets
(“logical” since they reside within a single physical device).
The IMCH internal registers (I/O Mapped and Configuration registers) are accessible by
the IA-32 core. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit)
quantities, with the exception of CONFIG_ADDRESS, which can only be accessed as a
Dword. All multi-byte numeric fields use “little-endian” ordering (i.e., lower addresses
contain the least significant parts of the field).
Irrespective of the access mechanism used (I/O register mechanism, or memory-
mapped mechanism), the IMCH ONLY supports 1-4 byte accesses into configuration
space. Software must (if necessary) take steps to prevent use of opcodes that would
treat configuration space destinations as objects greater than a single Dword (32 bits)
in size. Such attempted usage will result in spurious behavior up to and including
hanging the platform.
Some of the IMCH registers described in this section contain reserved bits which are
labeled “Reserved”. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note the software does not need to perform read, merge, write
operation for the configuration address register.
In addition to reserved bits within a register, the IMCH contains address locations in the
configuration space of the Host-NSI Bridge entity that are marked either “Reserved” or
“Intel Reserved”. The IMCH responds to accesses to “Reserved” address locations by
completing the host cycle. When a “Reserved” register location is read, a zero value is
returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Write operations to
“Reserved” registers have no effect on the IMCH. Registers that are marked as “Intel
Reserved” must not be modified by system software. Writes to “Intel Reserved”
registers may cause system failure. Reads to “Intel Reserved” registers may return a
non-zero value.
Upon a Reset, CMI sets its entire internal configuration registers to predetermined
default states. At reset, some register values are determined by external strapping
options. A register’s default value represents the minimum functionality feature set
required to successfully bring up the system. It is the responsibility of the system
initialization software (usually the BIOS) to properly determine the DRAM
configurations, operating parameters and optional system features that are applicable,
and to program CMI registers accordingly.
IMCH Sticky Registers
Certain registers in the IMCH are sticky through a hard-reset. They will only be reset on
a Power-good reset. In general, these registers are the error logging registers and a
few special cases. The error command registers are not sticky, so that on reset bogus
errors are not reported and that errors are not reported through a mechanism that
hasn’t been set up in code yet. Only those registers that are explicitly marked as
“Sticky: YES” are sticky. Those not marked or those marked as NO are not sticky.
The following registers are sticky:
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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