EP80579 Datasheet, PDF (467/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-73. Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 5Ch
Offset End: 5Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
13
12
11
10
09
08
07
06
05
04 : 03
02
01
00
Generate MCERR for NSI Error 13: Generate MCERR
whenever bit 13 of NSI _FERR or NSI _NERR is set.
RNRO_MCERR _{0 = Disable}
1 = Enable
Generate MCERR for NSI Error 12: Generate MCERR
whenever bit 12 of NSI _FERR or NSI _NERR is set.
BDLLP_MCERR _{0 = Disable}
1 = Enable
BTLP_MCERR
Generate MCERR for NSI Error 11: Generate MCERR
whenever bit 11 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved Reserved
Generate MCERR for NSI Error 9: Generate MCERR
whenever bit 9 of NSI _FERR or NSI _NERR is set.
RCVRE_MCERR _{0 = Disable}
1 = Enable
Reserved Reserved
Generate MCERR for NSI Error 7: Generate MCERR
whenever bit 7 of NSI _FERR or NSI _NERR is set.
FEMR_MCERR _{0 = Disable}
1 = Enable
Generate MCERR for NSI Error 6: Generate MCERR
whenever bit 6 of NSI _FERR or NSI _NERR is set.
NEMR_MCERR _{0 = Disable}
1 = Enable
Generate MCERR for NSI Error 5: Generate MCERR
whenever bit 5 of NSI _FERR or NSI _NERR is set.
CEMR_MCERR _{0 = Disable}
1 = Enable
Reserved Reserved
PED_MCERR
Generate MCERR for NSI Error 2: Generate MCERR
whenever bit 2 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved Reserved
LD_MCERR
Generate MCERR for NSI Error 0: Generate MCERR
whenever bit 0 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Sticky
Bit Reset
Value
Bit Access
0b
RW
0b
RW
0b
RW
0b
0b
RW
0b
0b
RW
0b
RW
0b
RW
0b
0b
RW
0b
0b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
467