EP80579 Datasheet, PDF (195/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.2
IMCH Error Reporting Registers: Bus 0, Device 0, Function 1
The IMCH includes the registers listed in Table 7-12. These registers materialize in PCI
configuration space. See Section 16.2, “DRAM Controller Error Reporting Registers: Bus
0, Device 0, Function 1” for detailed discussion of these registers.
Table 7-12. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
0Ah
0Bh
0Dh
0Eh
2Ch
2Eh
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
62h
64h
68h
6Ah
6Ch
6Eh
70h
72h
74h
78h
7Ah
7Ch
01h
03h
05h
07h
08h
0Ah
0Bh
0Dh
0Eh
2Dh
2Fh
43h
47h
4Bh
4Fh
53h
57h
5Bh
5Fh
61h
63h
65h
69h
6Bh
6Dh
6Fh
70h
72h
74h
78h
7Ah
7Ch
“Offset 00h: VID - Vendor Identification Register” on page 447
8086h
“Offset 02h: DID - Device Identification Register” on page 447
5021h
“Offset 04h: PCICMD - PCI Command Register” on page 448
0000h
“Offset 06h: PCISTS - PCI Status Register” on page 448
0000h
“Offset 08h: RID - Revision Identification Register” on page 449
Variable
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 449
00h
“Offset 0Bh: BCC - Base Class Code Register” on page 449
FFh
“Offset 0Dh: MLT - Master Latency Timer Register” on page 450
00h
“Offset 0Eh: HDR - Header Type Register” on page 450
00h
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 450
0000h
“Offset 2Eh: SID - Subsystem Identification Register” on page 451
0000h
“Offset 40h: GLOBAL_FERR - Global First Error Register” on page 451
00000000h
“Offset 44h: GLOBAL_NERR - Global Next Error Register” on page 453
00000000h
“Offset 48h: NSI_FERR - NSI First Error Register” on page 454
00000000h
“Offset 4Ch: NSI_NERR - NSI Next Error Register” on page 457
00000000h
“Offset 50h: NSI_SCICMD - NSI SCI Command Register” on page 459
00000000h
“Offset 54h: NSI_SMICMD: NSI SMI Command Register” on page 461
00000000h
“Offset 58h: NSI_SERRCMD - NSI SERR Command Register” on page 464
00000000h
“Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register” on page 466
00000000h
“Offset 60h: FSB_FERR - FSB First Error Register” on page 468
0000h
“Offset 62h: FSB_NERR - FSB Next Error Register” on page 469
0000h
“Offset 64h: FSB_EMASK - FSB Error Mask Register” on page 470
0009h
“offset 68h: FSB_SCICMD - FSB SCI Command Register” on page 471
0000h
“Offset 6Ah: FSB_SMICMD - FSB SMI Command Register” on page 472
0000h
“Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register” on page 473
0000h
“Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register” on page 474
0000h
“Offset 70h: BUF_FERR - Memory Buffer First Error Register” on page 475
00h
“Offset 72h: BUF_NERR - Memory Buffer Next Error Register” on page 475
00h
“Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register” on page 476
00h
“Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register” on page 477 00h
“Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register” on page 478 00h
“Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register” on
page 479
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
195