EP80579 Datasheet, PDF (588/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.73 Offset 144h: PEAMASKERR - PCI Express* Unit Mask Error Register
This register is used for selecting the global error reporting method for the various error conditions.
Table 16-212.Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register (Sheet 1
of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 144h
Offset End: 147h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 144h
Offset End: 147h
Size: 32 bit
Default: 0000E000h
Power Well: Core
Bit Range
31 : 16
15
14
13
12
11
10
09
08
07
06
05
04
03
Bit Acronym
Bit Description
Sticky
Reserved For future additions.
Upstream Posted Queue Overflow Mask: Defaults to
masked, normally reported through PCI Express* receive
UPQOM ^{overflow status bit.}
Y
0 = Enable upstream posted queue overflow reporting.
1 = Disable upstream posted queue overflow reporting.
Upstream Non-Posted Queue Overflow Mask: Defaults
to masked, normally reported through PCI Express*
receive overflow status bit.
UNPQOM 0 = Enable upstream non-posted queue overflow
Y
reporting.
1 = Disable upstream non-posted queue overflow
reporting.
Upstream Completion Queue Overflow Mask: Defaults
to masked, normally reported through PCI Express*
receive overflow status bit.
UCQOM 0 = Enable upstream completion queue overflow
Y
reporting.
1 = Disable upstream completion queue overflow
reporting.
LLE Protocol Error Mask:
LPEM
0 = Enable LLE protocol error reporting.
Y
1 = Disable LLE protocol error reporting.
Link Down Error Mask: Mask reporting of detected link
transitions from DL_UP to DL_DOWN.
LDEM
0 = Enable link down error mask reporting.
Y
1 = Disable link down error mask reporting.
Downstream Data Queue Parity Error Reporting
Mask:
DDQPERM _{0 = Enable}
Y
1 = Disable
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Common Block Parity Reporting Mask :
CommBlk-
PARRM
0 = Enable CommBlkPAR reporting.
Y
1 = Disable CommBlkPAR reporting.
Reserved Reserved
Bit Reset
Value
0000h
1b
1b
1b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
588
August 2009
Order Number: 320066-003US