EP80579 Datasheet, PDF (725/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
18.4.4
18.4.5
Note:
Note:
18.4.6
5. The SMI handler can then:
a. Read the TIMEOUT bit in the TCO_STS register to check that the SMI# was
caused by the TCO timer. The SMI handler must also clear the TIMEOUT bit.
b. Write to the TCO_RLD register to reload the timer to make sure the TCO timer
does not reach 0 again.
c. Attempt to recover. May need to periodically reload the TCO timer.
The exact recovery algorithm is system-specific.
If the SMI handler was not able to clear the TIMEOUT bit and write to the TCO_RLD
register, the timer reaches zero a second time approximately 2.4 s later. At that point,
the hardware is assumed to be locked up, and the timer reads zero a second time,
which causes the SECOND_TO_STS bit to be set. At that point the logic resets the
platform if the reboots are enabled.
Handling a CPU or Other Hardware Lockup
If after the TIMEOUT SMI is generated, and the TCO timer again reaches 0, and reboots
are enabled, the System Management logic resets (and reboot) the system. This is in
the case where the CPU or other system hardware is locked up. During every boot,
BIOS must read the SECOND_TO_STS bit in the TCO_STS register to see if this is
normal boot or a reboot due to the timeout. The BIOS may also check the OS_POLICY
bits to see if it should try another boot or shutdown.
Handling an Intruder
The CMI has an input signal, INTRUDER#, that can be attached to a switch that is
activated by the system’s case being open. This input has a two RTC clock debounce. If
INTRUDER# goes active (after the debouncer), this sets the INTRD_DET bit in the
TCO_STS register. INTRUDER# can go active in any power state.
The INTRD_SEL bits in the TCO_CNT register can enable the CMI to cause an SMI# or
TCO interrupt. The software can also directly read the status of the INTRUDER# signal
(high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to
be used as a GPI if the intruder function is not required.
The INTRD_DET bit resides in the CMI’s RTC well, and is set and cleared synchronously
with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a
one to the bit location) there may be as much as two RTC clocks (about 65 µs) delay
before the bit is actually cleared. Also, the INTRUDER# signal must be asserted for a
minimum of 1 ms to guarantee that the INTRD_DET bit is set.
If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET
bit, the bit remains set and the SMI is generated again immediately. The SMI handler
can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal
goes inactive and then active again, there is not further SMIs, since the INTRD_SEL bits
would select that no SMI# be generated.
Handling a Potentially Failing Power Supply
It may be possible to detect that a power supply may fail in the near future by
monitoring its voltages for fluctuations. To support such an application, external A/Ds
with programmable thresholds could be included via SMBus/I²C. Upon receiving the
SMBus/I²C message, the CMI can generate an SMI or interrupt. The SMI handler (or
operating system-based extension) could then attempt to send a message before the
power completely fails.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
725