EP80579 Datasheet, PDF (1590/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.6.1.4
Offset 0000000Ch: ErrorStatus - Error Status Indicators
Status indicators are provided to report the CAN controller error state, receive error
count and transmit error count. Special flags to report error counter values equal to or
in excess of 96 errors are available to indicate heavily disturbed bus situations.
Table 39-9. Offset 0000000Ch: ErrorStatus - Error Status Indicators
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
Offset Start: 0000000Ch
Offset End: 0000000Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
Offset Start: 0000000Ch
Offset End: 0000000Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :20
19
18
17 :16
15 :8
07 :00
Bit Acronym
Bit Description
Sticky
RSVD
Reserved, these bits are always 0
rxgte96 The receiver error counter is greater or equal 96(dec)
txgte96 The transmitter error counter is greater or equal 96(dec)
The error state of the CAN node (bits[1:0]):
error_stat_1_0
“00” = error active (normal operation)
“01” = error passive
“1x” = bus off
The receiver error counter (bits [7:0]) according to the
rx_err_cnt_7_0 Bosch CAN 2.0 specification. When in bus off (inactive),
this counter is used to count the idle states
The transmitter error counter (bits [7:0]) according to the
tx_err_cnt_7_0 Bosch* CAN 2.0 specification. When it is greater than
255(dec), it is fixed at 255.
Bit Reset
Value
0h
0b
0b
0h
0b
0b
Bit Access
RO
RO
RO
RO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1590
August 2009
Order Number: 320066-003US