EP80579 Datasheet, PDF (852/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-49. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration
Registers Mapped Through ABAR Memory BAR
Offset Start Offset End
Register ID - Description
Default
Value
00h
04h
08h
0Ch
10h
A0h
100h, 180h
104h, 184h
108h, 188h
10Ch, 18Ch
110h, 190h
114h, 194h
118h, 198h
120h, 1A0h
124h, 1A4h
128h, 1A8h
12Ch, 1ACh
130h, 1B0h
134h, 1B4h
138h, 1B8h
13Ch, 1BCh
03h
07h
0Bh
0Fh
13h
A3h
17Fh, 1FFh
107h, 187h
10Bh, 18Bh
10Fh, 18Fh
113h, 193h
117h, 197h
11Bh, 19Bh
123h, 1A3h
127h, 1A7h
12Bh, 1ABh
12Fh, 1AFh
133h, 1B3h
137h, 1B7h
13Bh, 1BBh
13Fh, 1BFh
“Offset 00h: HCAP – HBA Capabilities Register” on page 853
Variable
“Offset 04h: GHC – Global HBA Control Register” on page 855
00000000h
“Offset 08h: IS – Interrupt Status Register” on page 856
00000000h
“Offset 0Ch: PI – Ports Implemented Register” on page 856
00000000h
“Offset 10h: VS – AHCI Version Register” on page 857
00010100h
“Offset A0h: SGPO -SPGIO Control Register” on page 857
00000000h
“Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register” on
page 858
Variable
“Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Register” on
page 858
Variable
“Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register” on page 859
Variable
“Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits Register”
on page 859
Variable
“Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register” on page 860
00000000h
“Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register” on page 861
00000000h
“Offset 118h: PxCMD[0-1] – Port [0-1] Command Register” on page 863
Variable
“Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register” on page 866
0000007Fh
“Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register” on page 867
FFFFFFFFh
“Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register” on page 868 Variable
“Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register” on page 869 00000000h
“Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register” on page 870 00000000h
“Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register” on page 872 00000000h
“Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register” on page 872
00000000h
“Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register” on page 873
00000000h
23.3.1 Generic Host Controller
Start
00
04
08
0C
10
End
03
07
0B
0F
13
Symbol
HCAP
GHC
IS
PI
VS
Host Capabilities
Global Host Control
Interrupt Status
Ports Implemented
Version
Description
Intel^® EP80579 Integrated Processor Product Line Datasheet
852
August 2009
Order Number: 320066-003US