EP80579 Datasheet, PDF (1130/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.6.3
30.2.6.4
30.2.6.5
30.2.6.6
Automatic Rotation Mode (Equal Priority Devices)
In some applications, there are a number of interrupting devices of equal priority.
Automatic rotation mode provides for a sequential eight-way rotation. In this mode, a
device receives the lowest priority after being serviced. In the worst case, a device
requesting an interrupt has to wait until each of seven other devices are serviced at
most once.
There are two ways to accomplish automatic rotation using OCW2; the Rotation on
Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI Mode
which is set by (R=1, SL=0, EOI=0).
Specific Rotation Mode (Specific Priority)
Software can change interrupt priorities by programming the bottom priority. For
example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest
priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:
R=1, SL=1, and LO-L2 is the binary priority level code of the bottom priority device.
In this mode, internal status is updated by software control during OCW2. However, it
is independent of the EOI command. Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1
and LO-L2=IRQ level to receive bottom priority.
Poll Mode
Poll Mode can be used to conserve space in the interrupt vector table. Multiple
interrupts that can be serviced by one interrupt service routine do not need separate
vectors if the service routine uses the poll command. Polled Mode can also be used to
expand the number of interrupts. The polling interrupt service routine can call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll Command.
The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read will contain a ‘1’ in bit 7 if there is an interrupt, and the
binary code of the highest priority level in bits 2:0.
Edge and Level Triggered Mode
In ISA (legacy) systems this mode is programmed using bit 3 in ICW1, which sets level
or edge for the entire controller. In the IICH, this bit is disabled and a new register for
edge and level triggered mode selection, per interrupt input, is included. This is the
Edge/Level control Registers ELCR1 and ELCR2.
If an ELCR bit is ‘0’, an interrupt request is recognized by a low to high transition on the
corresponding IRQ input. The IRQ input can remain high without generating another
interrupt. If an ELCR bit is ‘1’, an interrupt request is recognized by a high level on the
corresponding IRQ input and there is no need for an edge detection. The interrupt
request must be removed before the EOI command is issued to prevent a second
interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1130
August 2009
Order Number: 320066-003US