EP80579 Datasheet, PDF (1528/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-119.TOTH: Total Octets Transmitted High Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40CCh
Offset End: 40CFh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40CCh
Offset End: 40CFh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40CCh
Offset End: 40CFh
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 00
TOTH
Number of total octets transmitted - upper 4 bytes
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.42 TPR – Total Packets Received Register
This register counts the total number of all packets received by the node (must pass
the MAC address filtering - Broadcast or Individual-Address/Multicast match). All
packets received by the MAC will be counted in this register, regardless of their length,
whether they encountered errors, and regardless of whether they are detected as
regular packets or flow control packets.
Table 37-120.TPR: Total Packets Received Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40D0h
Offset End: 40D3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40D0h
Offset End: 40D3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40D0h
Offset End: 40D3h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 00
TPR
Total of all packets received
Sticky
Bit Reset
Value
0h
Bit Access
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1528
August 2009
Order Number: 320066-003US