EP80579 Datasheet, PDF (1725/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
46.2.3
XOR Chains
XOR Chains are used to validate connectivity of high speed IO pins when JTAG control
is unavailable. This technique chains together pins in a serial fashion, with an XOR gate
between each pin, effectively creating a single multi-input XOR gate. By toggling the
pins individually or in combination, the connectivity of the pins at the platform level,
and the functionality of the I/O driver itself can be validated.
There is only one XOR chain in to cover the AFEs of PCI express, SATA and USB. This
mode can be entered by setting bit 8 of test control register 0.
Table 46-3. XOR Chains
XOR Chain Order
PEA0_Rn[6]
PEA0_Rp[6]
PEA0_Tp[6]
PEA0_Tn[6]
PEA0_Rn[7]
PEA0_Rp[7]
PEA0_Tp[7]
PEA0_Tn[7]
PEA0_Rn[4]
PEA0_Rp[4]
PEA0_Tp[4]
PEA0_Tn[4]
PEA0_Rn[5]
PEA0_Rp[5]
PEA0_Tp[5]
PEA0_Tn[5]
PEA_RCOMPO
PEA_ICOMPO
PEA0_Rn[2]
PEA0_Rp[2]
PEA0_Tp[2]
PEA0_Tn[2]
PEA0_Rn[3]
PEA0_Rp[3]
PEA0_Tp[3]
PEA0_Tn[3]
PEA0_Rn[0]
PEA0_Rp[0]
PEA0_Tp[0]
PEA0_Tn[0]
PEA0_Rn[1]
PEA0_Rp[1]
Comments
First pin / input pin to XOR
chain
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1725