EP80579 Datasheet, PDF (48/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
46.2.3 XOR Chains ........................................................................................ 1725
Technical Specifications, Volume 6 of 6..................................... 1727
47.0 SKUs, Power Savings and Pre-Boot Firmware ...................................................... 1729
47.1 Overview ...................................................................................................... 1729
47.2 SKUs, Strap Options and Pre-Boot Firmware Programmable Configuration Modes ... 1729
47.2.1 SKU Features ....................................................................................... 1729
47.2.2 DDR2 Frequencies Supported by the EP80579 .......................................... 1731
47.2.3 Strap Options (Platform-based Configuration)........................................... 1731
47.2.4 Pre-Boot Firmware Programmable SKU Options ........................................ 1732
48.0 Package Specifications......................................................................................... 1733
48.1 Package Introduction ..................................................................................... 1733
48.2 Functional Signal Definitions............................................................................ 1733
48.3 JTAG Boundary Scan Chain (BSC) and XOR Chain .............................................. 1733
48.4 Signal Pin Descriptions ................................................................................... 1734
48.4.1 IA-32 Core .......................................................................................... 1736
48.4.1.1
48.4.1.2
48.4.1.3
Thermal Diode .............................................................................. 1736
Global Clock CRU .......................................................................... 1736
Sideband Miscellaneous Signals....................................................... 1737
48.4.2 Integrated Memory Controller Hub (IMCH) ............................................... 1739
48.4.2.1
48.4.2.2
48.4.2.3
IMCH Reset .................................................................................. 1739
DDR2 SDRAM ............................................................................... 1739
PCI Express* ................................................................................ 1741
48.4.3 Integrated I/O Controller Hub (IICH)....................................................... 1744
48.4.3.1
48.4.3.2
48.4.3.3
48.4.3.4
48.4.3.5
48.4.3.6
48.4.3.7
48.4.3.8
48.4.3.9
48.4.3.10
Real Time Clock ............................................................................ 1744
General Purpose I/O (GPIO) and Interrupts ...................................... 1744
Serial Peripheral Interface (SPI) ...................................................... 1749
Low Pin Count (LPC) Interface......................................................... 1749
SMBus ......................................................................................... 1750
UART Interface ............................................................................. 1751
Serial ATA (SATA) Interface............................................................ 1753
Universal Serial Bus (USB) Interface ................................................ 1755
Power Management Interface.......................................................... 1756
IICH Miscellaneous Signals ............................................................. 1758
48.4.4 Acceleration and I/O Complex (AIOC)...................................................... 1759
48.4.4.1
48.4.4.2
48.4.4.3
48.4.4.4
48.4.4.5
48.4.4.6
Controller Area Network (CAN) Bus.................................................. 1759
Gigabit Ethernet (GbE) Interface ..................................................... 1760
Time Division Multiplexing (TDM) Interface ....................................... 1764
Local Expansion Bus (LEB) Interface ................................................ 1765
Synchronous Serial Port (SSP) Interface........................................... 1768
IEEE 1588-2008 Hardware Assist Interface ....................................... 1768
48.4.5 Miscellaneous....................................................................................... 1769
48.4.5.1
48.4.5.2
48.4.5.3
48.4.5.4
JTAG ........................................................................................... 1769
Miscellaneous Signals .................................................................... 1770
Reserved ..................................................................................... 1770
No Connect .................................................................................. 1771
48.4.6 Power ................................................................................................. 1772
48.5 Flip-Chip Ball Grid Array (FCBGA) Package Dimensions ....................................... 1773
48.6 Ball Map Information ...................................................................................... 1778
49.0 Electrical Specifications ....................................................................................... 1819
49.1 Absolute Maximum Ratings ............................................................................. 1820
49.1.1 Input and I/O Pin Undershoot and Overshoot Specifications........................ 1820
49.2 Power Characteristics ..................................................................................... 1823
49.2.1 Power Supply Requirements................................................................... 1823
Intel^® EP80579 Integrated Processor Product Line Datasheet
48
August 2009
Order Number: 320066-003US