EP80579 Datasheet, PDF (80/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
37-14
37-15
37-16
37-17
37-18
37-19
37-20
37-21
37-22
37-23
37-24
37-25
37-26
37-27
37-28
37-29
37-30
37-31
37-32
37-33
37-34
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37-38
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37-40
37-41
37-42
37-43
37-44
37-45
37-46
37-47
37-48
37-49
37-50
37-51
37-52
37-53
37-54
37-55
37-56
37-57
37-58
37-59
37-60
37-61
37-62
37-63
37-64
37-65
GbE Reset Effects ........................................................................................... 1421
Long Word Little Endian, Byte Little Endian Ordering ........................................... 1423
Endianness Control for Gigabit Ethernet MACs .................................................... 1423
Endianness Mode 0: Long Word Little Endian, Byte Big Endian .............................. 1423
Endianness Mode 1: Long Word Little Endian, Byte Little Endian (Default) .............. 1423
Endianness Mode 2: Long Word Big Endian, Byte Big Endian................................. 1424
Endianness Mode 3: Long Word Big Endian, Byte Little Endian .............................. 1424
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ......................................................................... 1425
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ......................................................................... 1429
Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ......................................................................... 1432
I/O Mapped Registers...................................................................................... 1436
CTRL: Device Control Register ........................................................................ 1438
STATUS: Device Status Register ..................................................................... 1441
CTRL_EXT: Extended Device Control Register ................................................... 1442
CTRL_AUX: Auxiliary Device Control Register .................................................... 1444
EEPROM_CTRL - EEPROM Control Register ....................................................... 1446
EEPROM_RR – EEPROM Read Register ............................................................... 1448
FCAL: Flow Control Address Low Register ......................................................... 1449
FCAH: Flow Control Address High Register ....................................................... 1450
FCT: Flow Control Type Register ..................................................................... 1451
VET: VLAN EtherType Register ........................................................................ 1452
FCTTV: Flow Control Transmit Timer Value Register ........................................... 1452
PBA: Packet Buffer Allocation Register ............................................................. 1453
ICR0: Interrupt 0 Cause Read Register ............................................................ 1454
ITR0: Interrupt 0 Throttling Register ............................................................... 1457
ICS0: Interrupt 0 Cause Set Register .............................................................. 1458
IMS0: Interrupt 0 Mask Set/Read Register ....................................................... 1459
IMC0: Interrupt 0 Mask Clear Register ............................................................. 1460
ICR1: Interrupt 1Cause Read Register ............................................................. 1462
ICS1: Interrupt 0 Cause Set Register .............................................................. 1464
IMS1: Interrupt 1 Mask Set/Read Register ....................................................... 1466
IMC1: Interrupt 1 Mask Clear Register ............................................................. 1467
ICR2: Error Interrupt Cause Read Register ....................................................... 1469
ICS2: Error Interrupt Cause Set Register ......................................................... 1471
IMS2: Error Interrupt Mask Set/Read Register ................................................... 1472
IMC2: Error Interrupt Mask Clear Register ......................................................... 1473
RCTL: Receive Control Register ....................................................................... 1474
FCRTL: Flow Control Receive Threshold Low Register .......................................... 1478
FCRTH: Flow Control Receive Threshold High Register ........................................ 1479
RDBAL: Receive Descriptor Base Address Low Register ...................................... 1480
RDBAH: Receive Descriptor Base Address High Register ..................................... 1480
RDLEN: Receive Descriptor Length Register ...................................................... 1481
RDH: Receive Descriptor Head Register ........................................................... 1481
RDT: Receive Descriptor Tail Register .............................................................. 1482
RDTR: RX Interrupt Delay Timer (Packet Timer) Register ................................... 1483
RXDCTL: Receive Descriptor Control Register ................................................... 1483
RADV: Receive Interrupt Absolute Delay Timer Register ..................................... 1485
RSRPD: Receive Small Packet Detect Interrupt Register ..................................... 1486
RXCSUM: Receive Checksum Control Register ................................................... 1487
MTA[0-127] – 128 Multicast Table Array Registers ............................................ 1488
RAL[0-15] - Receive Address Low Register ....................................................... 1488
RAH[0-15] - Receive Address High Register ...................................................... 1489
Intel^® EP80579 Integrated Processor Product Line Datasheet
80
August 2009
Order Number: 320066-003US