EP80579 Datasheet, PDF (1011/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-41. Offset 24h: USB2STS - USB 2.0 Status Register (Sheet 3 of 3)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 24h
Offset End: 27h
Size: 32 bit
Default: 00001000h
Power Well: Core
Bit Range
01
00
Bit Acronym
Bit Description
Sticky
USBERRINT
USBINT
USB Error Interrupt:
0 = No error condition.
1 = The Host Controller sets this bit to 1 when completion
of a USB transaction results in an error condition,
e.g., error counter underflow. If the TD on which the
error interrupt occurred also had its IOC bit set, both
this bit and Bit 0 are set. See the EHCI Specification
for a list of the USB errors that will result in this
interrupt being asserted.
USB Interrupt:
0 = No completion of a USB transaction whose Transfer
Descriptor had its IOC bit set. No short packet is
detected.
1 = The Host Controller sets this bit to 1 on the
completion of a USB transaction, which results in the
retirement of a Transfer Descriptor that had its IOC
bit set.
The Host Controller also sets this bit to 1 when a short
packet is detected (actual number of bytes received was
less than the expected number of bytes).
Bit Reset
Value
0h
0h
Bit Access
RWC
RWC
26.3.2.3
Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register
This register enables and disables reporting of the corresponding interrupt to the
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Interrupt sources that are disabled in this register still appear in
the Status Register to allow the software to poll for events.
Each interrupt enable bit description indicates whether it is dependent on the interrupt
threshold mechanism (see Section 4 of the EHCI Specification).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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