EP80579 Datasheet, PDF (1073/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-20. Offset 34h: SMI_STS - SMI Status Register (Sheet 3 of 3)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 34h
Offset End: 34h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
05
04
03
02
01 : 00
Bit Acronym
Bit Description
Sticky
APM_STS
SMI# was generated by a write access to the APM
control register and if the APMC_EN bit is set.
0 = No SMI# generated by write access to APM Control
register with APMCH_EN bit set.
1 = SMI# was generated by a write access to the APM
Control register with the APMC_EN bit set.
This bit is cleared by writing a one to its bit position.
SMI_ON_
SLP_EN_STS
This bit will be set when a write access attempts to set
the SLP_EN bit.
0 = No SMI# caused by write of 1 to SLP_EN bit when
SLP_SMI_EN bit is also set.
1 = Indicates an SMI# was caused by a write of 1 to
SLP_EN bit when SLP_SMI_EN bit is also set.
This bit is cleared by writing a 1 to this bit position.
LEGACY_
USB_STS
This non-sticky read-only bit is a logical OR of each of
the SMI status bits in the USB Legacy Keybd Register
ANDed with the corresponding enable bits. This bit will
not be active if the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
BIOS_STS
0 = No SMI# generated due to ACPI software
requesting attention.
1 = SMI# was generated due to ACPI software
requesting attention (writing a 1 to the GBL_RLS
bit with the BIOS_EN bit set).
Reserved Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RWC
RWC
RO
RWC
27.3.3.11 Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register
Table 27-21. Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 38h
Offset End: 38h
Size: 16 bit
Default: 0000h
Power Well: Resume
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
ALT_GPI_
SMI_EN
These bits are used to enable the corresponding GPIO to
cause an SMI#. In order for these bits to have any
effect, the following must be true.
1. The corresponding bit in the ALT_GPI_SMI_EN
register is set.
2. The corresponding GPI must be routed in the
GPI_ROUT register to cause an SMI.
3. The corresponding GPIO must be implemented.
All bits are in the resume well.
Bit Reset
Value
0000h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1073