EP80579 Datasheet, PDF (1232/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.35 Offset E2h: PMCSE – Power Management Control and Status Extension
Register
For an overview of the power management capability of AIOC devices, see Section
35.5, “Power Management of AIOC Devices” on page 1236.
Table 34-37. Offset E2h: PMCSE: Power Management Control and Status Extension Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: E2h
Offset End: E2h
Size: 8 bit
Default: 0000h
Power Well: Core
Bit Range
7
6
5 :0
Bit Acronym
Bit Description
Sticky
BPCC_EN
B2_B3_N
RSV
Bus Power/Clock Control Enable)- A “0” indicates that
the bus power/clock control policies have been disabled.
When the Bus Power/Clock Control mechanism is disabled,
the bridge’s PMCSR PowerState field cannot be used by
the system software to control the power or clock of the
bridge’s secondary bus.
B2/3 Support. With BPCC_EN a ‘0’ this bit is a don’t care
Reserved
Bit Reset
Value
0h
0b
0000b
Bit Access
RO
RO
RO
§§
Intel^® EP80579 Integrated Processor Product Line Datasheet
1232
August 2009
Order Number: 320066-003US