EP80579 Datasheet, PDF (1550/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Besides the reset change and capability advertisement, the EP80579 D3cold behavior is
identical to D3hot behavior (i.e. operates the same regardless of whether power is
supplied from main vs. auxiliary power supplies).
37.7.3 Power States
The GbE Controller supports D0 and D3 power states defined in the PCI Power
Management Specification. In addition, D0 is divided into two sub-states: D0u, and
D0a. In addition, it supports a Dr state that is entered when UNIT_RESET is asserted.
Figure 37-50 shows the power states and what causes a transition between them.
Figure 37-50.Power State Transitions
PWR_GOOD
assertion
UNIT_RESET
deassertion
Dr*
UNIT_RESET
assertion
D0u
UNIT_RESET
assertion
Set
Power State
to D0
Enable
Memory/IO Access
UNIT_RESET
assertion
D3
Set
Power State
To D3
* Equivalent to D3
D0a
37.7.3.1
Dr
On initial boot-up, once PWR_GOOD is asserted the GbE controller will enter the Dr
state and read the EEPROM. If the APM Enable bit in the EEPROM's Initialization Control
Word 2 is set then APM Wake Up will be enabled.
Internally, the controller treats the Dr reset state equivalently to D3. Any WakeUp filter
settings that were enabled before entering this reset state will be maintained.
The deassertion (falling edge) of UNIT_RESET will cause a transition to D0u.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1550
August 2009
Order Number: 320066-003US