EP80579 Datasheet, PDF (73/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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Offset B0h: CONFIG - Configuration Register ....................................................1040
Debug Port Behavior .......................................................................................1041
IMCH-IICH Messages ......................................................................................1046
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management PCI
Configuration Registers ....................................................................................1047
Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register ........................1047
Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register ........................1049
Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register .......................1051
Offset B8h: GPI_ROUT - GPI Routing Control Register .........................................1053
Summary of APM Registers Mapped in I/O Space.................................................1053
Offset B2h: APM_CNT - Advanced Power Management Control Port Register ...........1054
Offset B3h: APM_STS - Advanced Power Management Status Port Register .............1054
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management General
Configuration Registers Mapped Through PMBASE I/O BAR ...................................1055
Offset 00h: PM1_STS – Power Management 1 Status Register .............................1056
Offset 02h: PM1_EN - Power Management 1 Enables Register .............................1058
Offset 04h: PM1_CNT - Power Management 1 Control Register ............................1059
Offset 08h: PM1_TMR - Power Management 1 Timer Register ..............................1060
Offset 10h: PROC_CNT - Processor Control Register ...........................................1060
Offset 14h: LV2 - Level 2 Register ...................................................................1063
Offset 28h: GPE0_STS - General Purpose Event 0 Status Register ........................1063
Offset 2Ch: PMBASE_GPE0_EN - General Purpose Event 0 Enables Register ..........1067
Offset 30h: SMI_EN - SMI Control and Enable Register .......................................1068
Offset 34h: SMI_STS - SMI Status Register ......................................................1071
Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register .......................1073
Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register .....................1074
Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register ...........................................1074
Causes of SCI .................................................................................................1076
Causes of TCO SCI ..........................................................................................1076
Causes of SMI# .............................................................................................1077
Causes of TCO SMI#........................................................................................1078
Break Events .................................................................................................1079
C0→C2→C0 Timings .......................................................................................1082
Sleep State Output Conditions ..........................................................................1083
Sleep Types ...................................................................................................1084
Causes of Wake Events ...................................................................................1085
GPI Wake Events ............................................................................................1085
Transitions Due To Power Failure.......................................................................1086
Transitions Due to Power Button .......................................................................1088
Transitions Due to RI# Signal ...........................................................................1089
Write-Only Registers with Read Paths in Alternate Access Mode ............................1092
PIC Reserved Bits Return Values ......................................................................1093
Register Write Accesses in Alternate Access Mode................................................1094
IA-32 Core Interface Signal State ......................................................................1097
Summary of IA-32 Core Interface Registers Mapped in I/O Space ..........................1097
Offset 61h: NMI_STS_CNT - NMI Status and Control Register ..............................1098
Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index) Register ...............1099
Offset 92h: PORT92 - Fast A20 and Init Register ...............................................1100
Offset F0h: COPROC_ERR - Coprocessor Error Register ......................................1100
Offset CF9h: RST_CNT - Reset Control Register .................................................1101
INIT# Going Active .........................................................................................1102
NMI Sources...................................................................................................1103
I/O Registers ..................................................................................................1106
RTC (Standard) RAM Bank................................................................................1106
Summary of Real Time Clock Indexed Registers ..................................................1107
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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