EP80579 Datasheet, PDF (1753/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 48-16. UART Signals (Sheet 3 of 3)
Signal Name
SIU_TXD1
SIU_TXD2
IO Type
LVTTL,3.3V
LVTTL,3.3V
Direction
Ball
Count
I/O
1
I/O
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
BSC
UART Port 1 Serial Data Output: Serial data
output to the communication peripheral/modem
or data set for UART port 1. Upon reset, the TXD
pins will be set to MARKING condition (logic ‘1’
state).
UART Port 2 Serial Data Output: Serial data
output to the communication peripheral/modem
or data set for UART port 2. Upon reset, the TXD
pins will be set to MARKING condition (logic ‘1’
state).
GPIO IRQ Strap: This strap selects the interrupt
capabilities of some GPIO pins on the EP80579 .
The EP80579 interprets this strap as follows:
0 = GPIO IRQ capability enabled.
1 = GPIO IRQ capability disabled (default)
UART_CLK
LVTTL,3.3V I
1
TOTAL
17
BSC
UART CLock: Input clock to the SIU. This clock is
passed to the baud clock generation logic for the
UART in the SIU. The clock can run at either
14.7456, 33, or 48 MHz.
48.4.3.7 Serial ATA (SATA) Interface
Table 48-17. Serial ATA Interface Signals (Sheet 1 of 2)
Signal Name
SATA_TXp0
SATA_TXn0
SATA_RXp0
SATA_RXn0
SATA_CLKREFn
SATA_CLKREFp
SATA_TXp1
IO Type
LV Diff
LV Diff
LV Diff
LV Diff
CMOS
CMOS
LV Diff
Direction
Ball
Count
O
1
O
1
I
1
I
1
I
1
I
1
O
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
XOR
XOR
XOR
XOR
XOR
Serial ATA Interface Port 0 Transmit Data Pair
(Differential): The positive side of the port 0
transmit data pair.
Serial ATA Interface Port 0 Transmit Data Pair
(Differential): The negative side of the port 0
transmit data pair.
Serial ATA Interface Port 0 Receive Data Pair
(Differential): The positive side of the port 0
receive data pair.
Serial ATA Interface Port 0 Receive Data Pair
(Differential): The negative side of the port 0
receive data pair.
Serial ATA Reference Clock (Differential): The
negative side of the 100MHz clock input from
the clock generator for the SATA PLL.
Serial ATA Reference Clock (Differential): The
positive side of the 100MHz clock input from the
clock generator for the SATA PLL.
Serial ATA Interface Port 1 Transmit Data Pair
(Differential): The positive side of the port 1
transmit data pair.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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