EP80579 Datasheet, PDF (1177/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-12. Offset 00h: THR - Transmit Holding Register
Description:
View: IA F
Base Address: Base (IO) (DLAB = 0)
Offset Start: 00h
Offset End: 00h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
TB_7_0 Data byte received (bits [7:0]), least significant bit first
Bit Reset
Value
00h
Bit Access
WO
33.5.3.3
In FIFO mode, writing to THR puts data to the top of the FIFO. The data at the bottom
of the FIFO is loaded to the shift register when it is empty.
Offset 01h: IER - Interrupt Enable Register
This register enables five types of interrupts which independently activate the int signal
and set a value in the Interrupt Identification Register. Each of the five interrupt types
can be disabled by resetting the appropriate bit of the IER register. Similarly, by setting
the appropriate bits, selected interrupts can be enabled. Receiver time out interrupt
can be configured to be separated from the receive data available interrupt (using the
bit 5: COMP)
The use of bit 5 to bit 4 is different from the register definition of standard 16550.
Table 33-13. Offset 01h: IER - Interrupt Enable Register (Sheet 1 of 2)
Description:
View: IA F
Base Address: Base (IO) (DLAB = 0)
Offset Start: 01h
Offset End: 01h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :06
05
04
03
Bit Acronym
Bit Description
Sticky
RSVD
COMP
RTOIE
MIE
RSVD = 0
Compatibility Enable:
0 = Bit 0 of this register also controls RTOIE and bit 4 is
RSVD.
1 = Bit 4 of this register controls RTOIE.
Receiver Time Out Interrupt Enable:
0 = Receiver data Time out interrupt disabled
1 = Receiver data Time out interrupt enabled
Modem Interrupt Enable:
0 = Modem Status interrupt disabled
1 = Modem Status interrupt enabled
Bit Reset
Value
00h
0h
0h
0h
Bit Access
RO
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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