EP80579 Datasheet, PDF (1560/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
38.3.1.1
38.3.1.2
Two RCOMP pins are provided to establish the output driver impedance, one to control
the drive high strength, and one to control the drive low strength. These RCOMP
outputs drive into the external resistors provided by the customer. The drivers form a
resistor divider and the voltages developed in these dividers are compared to a
reference voltage. The RCOMP state machine independently adjusts the strength of the
drivers making them stronger or weaker until the comparator signals that the voltage is
greater than or less than the reference. The state machine will continue making
adjustments causing the comparators to oscillate between two strength settings just
above and just below the comparator trip point. Logic in the RCOMP state machine
recognizes when this "dithering" between the two values has begun, and holds the
strength output for the outputs fixed at one of the two settings. Note this algorithm is
independently and concurrently applied to the drive high strength and to the drive low
strength.
GbE
The GbE RCOMP controller starts operation when the GBE_AUX_PWR_GOOD input is
asserted. This condition indicates the power supply's are stable and it also indicates
that the GBE_REFCLK input is being driven with a 125 MHz clock. Refer to Section 37.0,
“Gigabit Ethernet Controller” on page 1341 for details on the GbE operation. The
GBE_REFCLK input is divided by either 4 or 16 and then used to drive the RCOMP state
machine. Also present are software accessible registers that provide options to
monitor/overwrite internal bias and comparator output for SV needs. See Section
38.4.1.5, “Offset 0x00000024h: GCU_GBE_RC_CTRL - GCU GbE RCOMP Control
Register” on page 1564 and Section 38.4.1.6, “Offset 0x00000044h:
GCU_GBE_RC_STAT - GCU GbE RCOMP Status Register” on page 1564.
LEB
The LEB RCOMP controller starts operation when the LEB comes out of reset. The
RCOMP logic is clocked by the externally provided expansion bus clock. Refer to Section
42.0, “Local Expansion Bus Controller” on page 1671 for details on the LEB operation.
Also present are software accessible registers that provide options to monitor/overwrite
internal bias and comparator output for SV needs. See Section 38.4.1.7, “Offset
0x00000050h: GCU_LEB_RC_STAT - GCU Local Expansion Bus RCOMP Status Register”
on page 1565 and Section 38.4.1.8, “Offset 0x00000054h: GCU_LEB_RC_CTRL - GCU
Local Expansion Bus RCOMP Control Register” on page 1566
Intel^® EP80579 Integrated Processor Product Line Datasheet
1560
August 2009
Order Number: 320066-003US