EP80579 Datasheet, PDF (1144/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.5.6
30.5.7
Special Notes on IRQ14 and IRQ15
IRQ14 and IRQ15 are special interrupts, used by the SATA controller when it is not
running in Native IDE mode. If in a legacy mode, IRQ14 and IRQ15 are not accepted
from the serial stream, and instead come from these controllers. If the controllers are
in Native mode, these interrupts are used by the interrupt controller.
Data Frame Format
Table 30-30 shows the format of the data frames for the associated interrupts. For the
legacy (PCI) interrupts (A–D), the output from the IICH is ANDed with the legacy (PCI)
input signal. This way, the interrupt can be signaled via both the legacy (PCI) interrupt
input signal and via the SERIRQ signal (they are shared).
Table 30-30. Data Frame Format
Data
Frame #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Interrupt
IRQ0
IRQ1
SMI#
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IOCHCK#
PCI INTA#
PCI INTB#
PCI INTC#
PCI INTD#
Clocks Past
Start Frame
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
Comment
Ignored. IRQ0 can only be generated via the internal 8524.
Before port 60h latch
Causes SMI# if low. Sets bit 15 in the SMI_STS register.
Ignored. IRQ8# can only be generated internally.
Before port 60h latch
Ignored. IRQ13 can only be generated from FERR#.
Not attached to PATA or SATA logic
Not attached to PATA or SATA logic
Same as ISA (legacy) IOCHCK# going active.
Drive PIRQA#
Drive PIRQB#
Drive PIRQC#
Drive PIRQD#
§§
Intel^® EP80579 Integrated Processor Product Line Datasheet
1144
August 2009
Order Number: 320066-003US