EP80579 Datasheet, PDF (836/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.4
Warning:
Note:
Message Signaled Interrupt Capability
The default values are defined with an h for hex, a bi for binary, or 00 for zero. If there
is not a letter following the default value, assume it is a binary number.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Reserved bits are Read Only.
23.1.4.1
Start
80
82
84
88
End
81
83
87
89
Symbol
MID
MC
MA
MD
Name
Message Signaled Interrupt Capability ID
Message Signaled Interrupt Message Control
Message Signaled Interrupt Message Address
Message Signaled Interrupt Message Data
Offset 80h: MID – Message Signaled Interrupt Identifiers Register
Table 23-28. Offset 80h: MID – Message Signaled Interrupt Identifiers Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 80h
Offset End: 81h
Size: 16 bit
Default: 7005h
Power Well: Core
Bit Range
15 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
NEXT
CID
Next Pointer (NEXT): Indicates the next item in the list
is the PCI power management pointer.
Capability ID (CID): Capabilities ID indicates MSI.
Bit Reset
Value
70h
05h
Bit Access
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
836
August 2009
Order Number: 320066-003US