EP80579 Datasheet, PDF (164/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 6-1. Powergood and Reset Interface
VSBY3_3
EP80579
DDR2 1.8V
2.5V for GbE
1.2V Logic Core
Ready ^EN
SILVERBOX_PWROK
PWRGD
1.0V/1.3V
EN IA-32 core
Ready
inverter
DB800
2ms
Delay
CK410
SYS_PWR_OK
100ms
Delay
CPU_VRD_PWR_GD
RSMRST#
GLUE 4
FP_RESET#
RESET_BTN
FP_PWRON#
PWRON_BTN
RTCRST#
RTC
Vccsus25
Vccpsus
Vccsus1
2.5V
GBE_aux_pwr_good
3.3V
1.2V
GBE Powergood
ITP/XDP
1k
PWRGD
NC8
RSTIN_N
PCI-E x8 conn
PWROK
VRMPWRGD
PLTRST_N
0 ohm empty
PCI-E switch
RSMRST_N
SYS_REST_N
PCIRST_N
PWRBTN_N
RTEST_N
WDT_N
PME_N
SYS_PWR_OK
GBE_AUX_PWR_GOOD
Wake signal
GBE_PME_WAKE
PCI-E x4
FWH
conn
LAI
SIO
LPC
P80
TPM
6.1.2.3
6.1.2.3.1
Reset and Powergood Distribution
The EP80579 reset follows a general path through the IICH to the IMCH and out to the
rest of the chip.
IICH
IICH plays the central role in reset and powergood distribution to the whole chip. IICH
receives two powergood signals from the platform (CPU_VRD_PWR_GD and
SYS_PWR_OK). The assertion of these signals starts the reset sequence for the
EP80579.
IICH generates the central reset signal (known as PLTRST#) that initiates the reset of
the rest of the chip. PLTRST# is received by IMCH. IICH also generates PCIRST# signal
for resetting the PCI device. PCIRST# is similar to PLTRST# except that PCIRST# can
be asserted using a CSR.
IICH also generates the powergood (CPUPWRGD#) signal for IA-32 core.
Intel^® EP80579 Integrated Processor Product Line Datasheet
164
August 2009
Order Number: 320066-003US