EP80579 Datasheet, PDF (1350/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Note:
37.4.3.7
37.4.3.8
37.4.3.9
Note:
• TCTL.CT = 0x0F
• TCTL.COLD = 0x200 (512d); for half-duplex mode
• TCTL.COLD = 0x040 (64d); for full-duplex mode
• TCTL.PSP = 1
Not all of these values are needed in all duplex modes, but it is more concise to simply
always program them to the values shown regardless of mode.
Program the Transmit IPG Register (TIPG) with the following values to get the minimum
legal inter packet gap (IPG):
• TIPG.IPGT = 0x8 (8d)
• TIPG.IPGR1 = 0x8 (8d)
• TIPG.IPGR2 = 0x6 (6d)
Not all of these values are needed in all duplex modes, but it is more concise to simply
always program them to the values shown regardless of mode.
Allocate a contiguous region of memory for the transmit descriptor list. Program the
transmit descriptor region into the following MMRs describing the memory region:
• Transmit Descriptor Base Address Low Register (TDBAL),
• Transmit Descriptor Base Address High Register (TDBAH),
• Transmit Descriptor Length Register (TDLEN),
• Transmit Descriptor Head Register (TDH), and
• Transmit Descriptor Tail Register (TDT).
Initialization of Statistics
Statistics registers are hardware-initialized to values as detailed in each particular
register's description. No initialization of these registers through software is necessary.
GbE Line Rate Configuration Change
The GbE unit must be reconfigured when switching rates with the RGMII gasket. The
following guidelines apply:
• Disable receiver and transmitter by setting the RCTL.EN and TCTL.EN bits to 0.
• Wait an appropriate time for any packet being received to finish.
• Write CTRL.SPEED, CTRL.FRCSPD, CTRL.FD, CTRL.FRCDPLX with the targeted
interface parameters.
• Re-enable receiver and transmitter by setting the RCTL.EN and TCTL.EN bits to 1.
Network Boot
Initialization of the GbE controller at power-up and/or reset from an optional serial
EEPROM is supported. Refer to Section 37.5.11, “Serial EEPROM” on page 1412 for
details on the use and configuration of the serial EEPROM.
Section 22.2.4 of the IEEE 802.3 specification requires that PHY devices enter a normal
operating state after power-up and/or reset without management intervention. As a
result, it is believed that the MAC is not required to perform any sort of PHY
initialization in the support of network boot.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1350
August 2009
Order Number: 320066-003US