EP80579 Datasheet, PDF (112/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 3-1. Device-Centric Logical View of EP80579 Devices
PCI Bus 0
PCI Host
Bridge
DRAM EDMA
USB
IA CPU
Transparent
PCI-to-PCI Bridge
PCI Bus M
IMCH / IICH Devices
ASU SSU
GbE
AIOC Devices
The on-die IMCH and IICH devices materialize on PCI bus 0 while the AIOC devices
materialize on PCI bus “M” that is behind a transparent PCI-to-PCI bridge on PCI bus 0
(the bus that the internal IMCH and IICH devices use). For simplicity, the figure does
not show external devices.
3.1.2
Terminology and Conventions
Throughout this chapter, we will use the generic term “device” to refer to either a PCI
device or a function of a PCI device. The text will be explicit when the distinction
between device and function is important.
Addresses are always in hexadecimal and broken into 16-bit segments, for example,
0_FEED_BEEF. When the distinction is important and not obvious, addresses are
subscripted with “V”, “P”, or “S” for virtual, physical, or system address spaces,
respectively.
The EP80579 addresses its DRAM in units of 8-byte quadwords. Before assigning byte
addresses to the byte lanes in DRAM, we will refer to the locations as byte lane A
through H as Table 3-1 illustrates.
Table 3-1.
Main Memory DRAM Organization
Address
0
8
16
Byte
Lane H
0H
8H
16H
Byte
Lane G
0G
8G
16G
Byte
Lane F
0F
8F
16F
Byte
Lane E
0E
8E
16E
Byte
Lane D
0D
8D
16D
Byte
Lane C
0C
8C
16C
Byte
Lane B
0B
8B
16B
Byte
Lane A
0A
8A
16A
The byte located in address 0, lane A is referred to as 0A, the byte in address 0 lane B
is 0B, etc.
Intel^® EP80579 Integrated Processor Product Line Datasheet
112
August 2009
Order Number: 320066-003US