EP80579 Datasheet, PDF (1229/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 34-32. Offset 3Eh: BCTL: Bridge Control Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 3Eh
Offset End: 3Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
05
MAMODE Master Abort Mode
04
VGA16
VGA 16-bit decode
03
VGAEN VGA Enable
02
ISAEN
ISA Enable
01
SERREN SERR# Enable
00
PREN
Parity Error Response Enable
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
0h
Bit Access
RO
RO
RW
RW
RW
RW
34.2.2.31 Offset DCh: PCID – Power Management Capability ID Register
For an overview of the power management capability of AIOC devices, see Section
35.5, “Power Management of AIOC Devices” on page 1236.
Table 34-33. Offset DCh: PCID: Power Management Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: DCh
Offset End: DCh
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
PCID
Capability ID: PCI SIG assigned capability record ID
(01h, power management capability)
Sticky
Bit Reset
Value
Bit Access
01h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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