EP80579 Datasheet, PDF (775/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1.11 Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register
Table 20-14. Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register
Description:
View: IA F 1^a Base Address: 0000h (IO)
Offset Start: 0Ch
Offset End: 0Ch
View: IA F 1 Base Address: 0000h (IO)
Offset Start: 1Ch
Offset End: 1Ch
View: IA F 2^b Base Address: 0000h (IO)
Offset Start: D8h
Offset End: D8h
View: IA F 2 Base Address: 0000h (IO)
Offset Start: D9h
Offset End: D9h
Size: 8 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 00
CBP
Clear Byte Pointer: Command is enabled with a write to
the I/O port address.
Writing to this register initializes the byte pointer flip/flop
to a known state. It clears the internal latch used to
address the upper or lower byte of the 16-bit Address and
Word Count Registers. The latch is also cleared by a part
reset and by the Master Clear command. This command
precedes the first access to a 16 bit DMA controller
register. The first access to a 16-bit register accesses the
least significant byte, and the second accesses the most
significant byte.
a. View 1 describes the control registers for Channels 0-3.
b. View 2 describes the control registers for Channels 4-7.
20.2.1.12 Offset 0Dh: DMA_MC - DMA Master Clear Register
Bit Reset
Value
X
Bit Access
WO
Table 20-15. Offset 0Dh: DMA_MC - DMA Master Clear Register
Description:
View: IA F 1^a Base Address: 0000h (IO)
Offset Start: 0Dh
Offset End: 0Dh
View: IA F 1 Base Address: 0000h (IO)
Offset Start: 1Dh
Offset End: 1Dh
View: IA F 2^b Base Address: 0000h (IO)
Offset Start: DAh
Offset End: DAh
View: IA F 2 Base Address: 0000h (IO)
Offset Start: DBh
Offset End: DBh
Size: 8 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 00
MSTCL
Master Clear: Enabled with a write to the port. This has
the same effect as the hardware Reset; Command,
Status, Request, and Byte Pointer flip/flop registers are
cleared and the Mask Register is set.
a. View 1 describes the control registers for Channels 0-3.
b. View 2 describes the control registers for Channels 4-7.
Bit Reset
Value
X
Bit Access
WO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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