EP80579 Datasheet, PDF (1105/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
29.0
29.1
Note:
29.2
Real Time Clock
Overview
The Real Time Clock (RTC) module provides a battery backed-up date and time keeping
device with two banks of static RAM with 128 bytes each. The first bank has 114 bytes
for general purpose usage. Three interrupt features are available: time of day alarm
with once a second to once a month range, periodic rates of 122 μs to 500 ms, and end
of update cycle notification. Seconds, minutes, hours, days, day of week, month, and
year are counted. Daylight savings compensation is optional. The hour is represented in
12 or 24 hour format, and data can be represented in BCD or binary format. The design
is meant to be functionally compatible with the Motorola* MS146818B. The time
keeping comes from a 32.768 KHz oscillating source, which is divided to achieve an
update every second. The lower 14 bytes on the lower RAM block have very specific
functions. The first ten are for time and date information. The next four (0Ah to 0Dh)
are registers, which configure and report RTC functions.
The time and calendar data must match the data mode (BCD or binary) and hour mode
(12 or 24 hour) as selected in register B. The programmer MUST make sure that data
stored in these registers is within the reasonable values ranges and represents a
possible date and time. The exception to these ranges is to store a value of C0 - FF in
the alarm bytes to indicate a “don’t care” situation. All alarm conditions must match to
trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled. The SET bit in
register B must be ‘1’ while programming these locations to avoid clashes with update
cycles. Access to time and date information is done through the RAM locations. If a
RAM read from the ten time and date bytes is attempted during an update cycle, the
value read will not necessarily represent the true contents of those locations. Any RAM
writes under the same conditions are ignored.
The leap year determination for adding a 29^th day to February does not take into
account the end-of-the-century exceptions. The logic simply assumes that all years
divisible by four are leap years. According to the Royal Observatory Greenwich, years
that are divisible by 100 are typically not leap years. In every fourth century (years
divisible by 400, like 2000), the 100-year-exception is overridden and a leap-year
occurs. Note that the year 2100 is the first time in which the current RTC
implementation would incorrectly calculate the leap-year.
RTC I/O Registers
The RTC internal registers and RAM are organized as two banks of 128 bytes each,
called the standard and extended banks. The first 14 bytes of the standard bank
contain the RTC time and date information along with four registers, A–D, that are used
for configuration of the RTC. The extended bank contains a full 128 bytes of battery
backed SRAM, and is accessible even when the RTC module is disabled (via the RTC
configuration register). Registers A – D do not physically exist in the RAM.
All data movement between the host CPU and the real-time clock is done through
registers mapped to the standard I/O space. The register map appears below in
Table 29-1.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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