EP80579 Datasheet, PDF (307/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.0
12.1
Enhanced Direct Memory Access Controller
(EDMA)
The IMCH includes an integrated four-channel Enhanced Direct Memory Access (EDMA)
controller to facilitate “push model” block transfers without IA-32 core intervention for
higher overall system performance. This section details the operating modes, setup,
interfaces, register set, and high-level implementation of the EDMA controller.
Overview
The EDMA engine provides a highly efficient means to move data within local system
memory or from the local system memory to the I/O subsystem. Each EDMA channel
provides low-latency, high-throughput data transfer capability with minimal IA-32 core
intervention. For the IA-32 core, it is a “fire and forget” type of memory transfer, with a
doorbell starting mechanism and interrupt capability for signaling completion.
Each channel optimizes block transfers of data through a linked-list descriptor chaining
mechanism that supports scatter/gather operations. Each channel is responsible for
providing the EDMA programming interface, executing the data transfers, and handling
any errors encountered during operation.
Each channel initiates traffic on both the local system memory and outbound traffic
arbiter interfaces, and is designed such that each independent channel is capable of
generating at least 1 GB/s of traffic during data hauls. In the absence of competition
from other traffic sources, multiple channels could theoretically saturate the local
memory interface. See Figure 12-1.
Each channel is independently enabled by setting the Start bit in the Control
Configuration Register. The Start bit is cleared after power-up or reset and
consequently the EDMA controller is disabled until software explicitly turns each one
on.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
307