EP80579 Datasheet, PDF (28/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
26.3.2 Host Controller Operational Register Details ............................................. 1005
26.3.2.1 Offset 20h: USB2CMD - USB 2.0 Command Register .......................... 1007
26.3.2.2 Offset 24h: USB2STS - USB 2.0 Status Register ................................ 1009
26.3.2.3 Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register ................. 1011
26.3.2.4 Offset 2Ch: FRINDEX - Frame Index Register .................................... 1013
26.3.2.5 Offset 30h: CTRLDSSEGMENT - Control Data Structure
Segment Register.......................................................................... 1013
26.3.2.6 Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register
1014
26.3.2.7 Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register .
1015
26.3.2.8 Offset 60h: CONFIGFLAG - Configure Flag Register ............................ 1015
26.3.2.9 Offset 64h: PORTSC - Port N Status and Control Register ................... 1016
26.4 EHC Initialization ........................................................................................... 1021
26.4.1 Power On ............................................................................................ 1021
26.4.2 Driver Initialization ............................................................................... 1021
26.4.3 EHC Resets .......................................................................................... 1021
26.5 Data Structures in Main Memory ...................................................................... 1022
26.6 USB 2.0 Enhanced Host Controller DMA ............................................................ 1022
26.6.1 Periodic List Execution........................................................................... 1022
26.6.1.1 Read Policies for Periodic DMA ........................................................ 1022
26.6.1.2 Write Policies for Periodic DMA ........................................................ 1024
26.6.2 Asynchronous List Execution .................................................................. 1025
26.6.2.1 Read Policies for Asynchronous DMA ................................................ 1025
26.6.2.2 Write Policies for Asynchronous DMA................................................ 1027
26.7 Data Encoding and Bit Stuffing ........................................................................ 1027
26.8 Packet Formats ............................................................................................. 1027
26.9 USB 2.0 Interrupts and Error Conditions ........................................................... 1027
26.9.1 Aborts on USB 2.0-Initiated Memory Reads .............................................. 1028
26.9.2 Host Interface Parity Errors ................................................................... 1028
26.10 USB 2.0 Power Management ........................................................................... 1030
26.10.1 Pause Feature ...................................................................................... 1030
26.10.2 Suspend Feature .................................................................................. 1031
26.10.3 ACPI Device States ............................................................................... 1031
26.10.4 ACPI System States .............................................................................. 1032
26.11 Interaction with Classic Host Controllers ........................................................... 1032
26.11.1 Port-Routing Logic ................................................................................ 1033
26.11.2 Device Connects ................................................................................... 1033
26.11.3 Device Disconnects ............................................................................... 1034
26.11.4 Effect of Resets on Port-Routing Logic ..................................................... 1034
26.12 USB 2.0 Legacy Keyboard Operation ................................................................ 1035
26.13 USB 2.0 Based Debug Port .............................................................................. 1035
26.13.1 USB 2.0 Based Debug Port Overview ....................................................... 1035
26.13.2 Debug Port Register Details ................................................................... 1036
26.13.2.1 Offset A0h: CNTL_STS - Control/Status Register ............................... 1036
26.13.2.2 Offset A4h: USBPID - USB PIDs Register .......................................... 1039
26.13.2.3 Offset A8h: DATABUF - Data Buffer Bytes 7:0 ................................... 1039
26.13.2.4 Offset B0h: CONFIG - Configuration Register .................................... 1040
26.13.3 USB 2.0 Based Debug Port Theory of Operation ........................................ 1040
26.13.3.1 Behavioral Rules ........................................................................... 1040
26.13.3.2 OUT Transactions .......................................................................... 1041
26.13.3.3 IN Transactions............................................................................. 1042
26.13.3.4 Debug Software ............................................................................ 1043
27.0 Power Management ............................................................................................. 1045
27.1 Features ....................................................................................................... 1045
27.2 IMCH-IICH Messages...................................................................................... 1046
Intel^® EP80579 Integrated Processor Product Line Datasheet
28
August 2009
Order Number: 320066-003US