EP80579 Datasheet, PDF (1396/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Software writes the non Auto-Negotiated PHY registers with the desired duplex
configuration and configures the MAC by to the same setting by programming
CTRL.FRCDPLX to 1 and CTRL.FD to the proper speed value (refer to “CTRL –
Device Control Register” on page 1438 for details).
Using PHY Registers
The driver may be required under some circumstances to read from, or write to, the
MII management registers in the PHY. These accesses are performed via the MDIO
registers in the GCU (refer to the GCU EAS Chapter for details). The MII registers allow
the driver to have direct control over the PHY's operation which may include:
• Resetting the PHY,
• Setting preferred link configuration for advertisement during the Auto-Negotiation
process,
• Restarting the Auto-Negotiation process,
• Reading Auto-Negotiation status from the PHY, and
• Forcing the PHY to a specific link configuration.
The set of PHY management registers required for all PHY devices may be found in the
IEEE P802.3ab draft standard.
Comments Regarding Forcing Link
Forcing link in GMII/MII mode requires the driver to configure both the MAC and PHY in
a consistent manner with respect to each other as well as the link partner. After
initialization, the driver configures the desired modes in the MAC, then accesses the
PHY registers to set the PHY to the same configuration.
Before enabling the link, the speed and duplex settings of the MAC may be forced by
software using the CTRL.FRCSPD, CTRL.FRCDPX, CTRL.SPEED, and CTRL.FD bits. After
the PHY and MAC have both been configured, the driver should write a 1 to the
CTRL.SLU bit.
37.5.8.4 10/100Mbps Specific Performance Enhancements
37.5.8.4.1
Adaptive IFS
The GbE supports back-to-back transmit Inter-Frame-Spacing (IFS) of 960 ns in 100
Mbit operation and 9.6 us in 10M bit operation. Although back-to-back transmission is
normally desirable, sometimes it can actually hurt performance in half-duplex
environments due to excessive collisions. Excessive collisions are likely to occur in
environments where one station is attempting to send large frames back-to-back, while
another station is attempting to send acknowledge (ACK) packets.
The GbE contains the AIT register that enables the implementation of a driver based
adaptive IFS algorithm for collision reduction, which is similar to Intel's other Ethernet
products (e.g. PRO/100 adapters). Refer to “AIT – Adaptive IFS Throttle Register” on
page 1495 for explicit details. Essentially, the Adaptive IFS throttles back-to-back
transmissions in the transmit MAC and delays their transfer to the CSMA/CD transmit
function, and thus can be used to delay the transmission of back-to-back packets on
the wire. Normally, this register should be set to 0. However, if additional delay is
desired between back-to-back transmits, then this register may be set with a value
greater than zero.
The AIT.AIFS provides a similar function to TIPG.IGPT (see “TIPG – Transmit IPG
Register” on page 1493). However this Adaptive IFS throttle register counts in units of
GTX/MTX_CLK clocks (which are 8ns, 80ns, 800ns for 10, 100, 1000 Mb/s mode
respectively), and is 16 bits wide, thus providing a greater maximum delay value.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1396
August 2009
Order Number: 320066-003US