EP80579 Datasheet, PDF (393/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.4
Offset 06h: PCISTS: PCI Status Register
PCISTS is a 16-bit status register that reports the occurrence of error events on Device
0’s PCI interface. Since IMCH Device 0 does not physically reside on a PCI bus many of
the bits are not supported.
Table 16-5. Offset 06h: PCISTS: PCI Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0010h
Power Well: Core
Bit Range
15
14
13
12
11
10 : 09
08
07
06 : 05
04
03 : 00
Bit Acronym
Bit Description
Sticky
DPE
SSE
RMAS
RTAS
STAS
Reserved
DPD
FB2B
Reserved
CLIST
Reserved
Detected Parity Error: This bit is set to 1 whenever it
receives a poisoned TLP regardless of the state of the
parity error response bit. Software may clear this by
writing a 1 to this bit.
Signaled System Error:
0 = Software clears this bit by writing a 1 to the bit
location.
1 = IMCH Device 0, Function 0 generates a SERR message
over NSI for any enabled Device 0, Function 0 error
condition. Device 0 error conditions are enabled in the
PCICMD register. Device 0 error flags are read/reset
from the PCISTS register.
The only error that can be enabled to signal system error
through Device 0, Function 0 is the detected parity error
which is essentially a NSI poisoned TLP.
Software may clear this by writing a 1 to this bit.
Received Master Abort Status: This bit is set if the IMCH
generates a NSI request that receives a completion with
unsupported request completion status. Software may
clear this by writing a 1 to this bit.
Received Target Abort Status:
Set to 1 by hardware if the IMCH generated a request that
received a completion with Completer Abort status.
Software clears this bit by writing a 1 to this bit location.
Signaled Target Abort Status: The IMCH does not
generate a Completer Abort on the NSI completion packet.
This bit is hardwired to w10. Writes to this bit position have
no effect.
Reserved
Master Data Parity Error Detected: This bit is hardwired
to 0.
Fast Back-to-Back: Reserved.
Reserved
Capability List: This bit is hardwired to 1 to indicate to
the configuration software that this device/function
implements a list of new capabilities. A list of new
capabilities is accessed via register CAPPTR at
configuration address offset 34h.
Reserved
Bit Reset
Value
0b
0b
0b
0b
0b
00b
0b
0b
00b
1b
0h
Bit Access
RWC
RWC
RWC
RWC
RO
RWC
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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