EP80579 Datasheet, PDF (1222/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.14 Offset 1Ah: SUBBNM – Subordinate Bus Number Register
Table 34-16. Offset 1Ah: SUBBNM: Subordinate Bus Number Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 1Ah
Offset End: 1Ah
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
SUBBNM Subordinate Bus Number
Sticky
Bit Reset
Value
0h
Bit Access
RW
34.2.2.15 Offset 1Bh: SECLT – Secondary Latency Timer Register
Table 34-17. Offset 1Bh: SECLT: Secondary Latency Timer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 1Bh
Offset End: 1Bh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
SECLT
Secondary Latency Timer
Sticky
Bit Reset
Value
0h
Bit Access
RO
34.2.2.16 Offset 1Ch: IOB – I/O Base Register
This register (together with IOBU) specifies the starting I/O address of devices in the
AIOC infrastructure. The range is aligned to a 4k boundary, so address bits [11:0] are
assumed to be zero.
Table 34-18. Offset 1Ch: IOB: I/O Base Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 1Ch
Offset End: 1Ch
Size: 8 bit
Default: F0
Power Well: Core
Bit Range
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
IOB
IOAW
These bits correspond to address bits [15:12] of the I/O
transaction. Address bits [13:16] are matched with IOBU.
The value “1” means that we implement 32-bit I/O space.
Bit Reset
Value
Fh
0
Bit Access
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1222
August 2009
Order Number: 320066-003US