EP80579 Datasheet, PDF (453/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.13 Offset 44h: GLOBAL_NERR - Global Next Error Register
The bit definitions are defined for GLOBAL_FERR.
Table 16-67. Offset 44h: GLOBAL_NERR - Global Next Error Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 44h
Offset End: 47h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 28
27
26
25
24
23
22
21 : 15
14
13
12
Bit Acronym
Bit Description
Sticky
Reserved Reserved
DRAM Controller Channel Fatal Error: This bit is sticky
through reset. System software clears this bit by writing a
DRAM_FE ^{1 to the location.}
Y
0 = No fatal DRAM I/F error.
1 = The IMCH detected a fatal DRAM interface error.
Host (FSB) Fatal Error: This bit is sticky through reset.
System software clears this bit by writing a 1 to the
FSB_FE ^location.
Y
0 = No fatal FSB error.
1 = The IMCH detected a fatal FSB error.
NSI Fatal Error: This bit is sticky through reset. System
software clears this bit by writing a 1 to the location.
NSI_FE
0 = No fatal NSI error.
Y
1 = The IMCH detected a fatal NSI error.
DMA Controller Fatal Error Device 1 fatal error
(EDMA): This bit is sticky through reset. System software
DMA_FE ^{clears this bit by writing a 1 to the location.}
Y
0 = No fatal DMA Controller error.
1 = The IMCH detected a fatal DMA controller error.
PA_FE
PCI Express* Port A(0) Fatal Error: This bit is sticky
through reset. System software clears this bit by writing a
1 to the location.
Y
0 = No fatal PCI Express Port A error.
1 = The IMCH detected a fatal PCI Express Port A(0) error.
PCI Express Port A1 Fatal Error This bit is sticky
through reset. System software clears this bit by writing a
PA1_FE
1 to the location.
Y
0 = No fatal PCI Express Port A1 error.
1 = The IMCH detected a fatal PCI Express Port A1 error.
Reserved Reserved
Buffer unit detected non-fatal error: This bit is sticky
through reset. System software clears this bit by writing a
BUFF_NFE ^{1 to the location.}
Y
0 = No non-fatal Buffer error.
1 = The IMCH detected a non-fatal Buffer error.
DRAM Controller Non-Fatal Error: This bit is sticky
through reset. System software clears this bit by writing a
DRAM_NFE ^{1 to the location.}
Y
0 = No non-fatal DRAM Controller error.
1 = The IMCH detected a non-fatal DRAM Controller error.
FSB Non-Fatal Error: This bit is sticky through reset.
System software clears this bit by writing a 1 to the
FSB_NFE ^location.
Y
0 = No non-fatal FSB error.
1 = The IMCH detected a non-fatal FSB error.
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
453