EP80579 Datasheet, PDF (1154/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Note:
• There are four possible memory address ranges beginning at:
1. FED0_0000h
2. FED0_1000h
3. FED0_2000h
4. FED0_3000h
• The choice of address ranges will be selected by configuration bits in the High
Performance Timer Configuration Register (in the memory-mapped chipset
configuration area) Table 17-26, “Offset 3404h: HPTC - High Performance Precision
Timer Configuration Register” on page 705.
• All registers are implemented in the Core well, and all bits are reset by PLTRST#.
• Reads to reserved registers or bits return a value of 0.
Reads to reserved registers or bits returns a value of 0.
Software must not attempt to lock the memory-mapped I/O ranges for High-Precision
Timers. If attempted, the lock is not honored, which means potential deadlock
conditions may occur.
Table 32-1. Summary of HPET Registers Mapped in Memory Space
Offset Start Offset End
Register ID - Description
000h
007h
“Offset 000h: GCAP_ID - General Capabilities and ID Register” on page 1155
010h
017h
“Offset 010h: GEN_CONF - General Configuration Register” on page 1156
020h
027h
“Offset 020h: GINTR_STA - General Interrupt Status Register” on page 1157
0F0h
100h at 20h
108h at 20h
0F7h
107h at 20h
10Fh at 20h
“Offset 0F0h: MAIN_CNT - Main Counter Value Register” on page 1158
“Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register” on
page 1159
“Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register” on page 1163
Default
Value
0429B17F808
6A201h
00000000000
00000h
00000000000
00000h
Xh
Xh
Xh
Intel^® EP80579 Integrated Processor Product Line Datasheet
1154
August 2009
Order Number: 320066-003US