EP80579 Datasheet, PDF (554/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-179.Offset 5Ch: MSIAR - MSI Address for PCI Express Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 5Ch
Offset End: 5Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 5Ch
Offset End: 5Fh
Size: 32 bit
Default: FEE00000h
Power Well: Core
Bit Range
03
02
01 : 00
Bit Acronym
Bit Description
Sticky
RH
DMMSIA
Reserved
Redirection Hint: Used by the IMCH to allow the interrupt
message to be redirected.
0 = Direct
1 = Redirect
Destination Mode: Used only if Redirection Hint is set to
‘1’.
0 = Physical
1 = Logical
Reserved
Bit Reset
Value
0b
0b
0b
Bit Access
RW
RW
16.4.1.41 Offset 60h: MSIDR - MSI Data Register
The MSI Data Register (MSIDR) contains all the data elated information to route MSI
interrupts.
Table 16-180.Offset 60h: MSIDR - MSI Data Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 60h
Offset End: 61h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 60h
Offset End: 61h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
14
13 : 12
Bit Acronym
Bit Description
Sticky
TM
DVS
Reserved
Trigger Mode: Same as the corresponding bit in the I/O
Redirection Table for that interrupt.
0 = Edge
1 = Level
Delivery Status: If using edge-triggered interrupts, this is
always a 1, since only assertion is sent. If using level-
triggered interrupts, then this bit indicates the state of the
interrupt input.
Reserved
Bit Reset
Value
0b
0b
0b
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
554
August 2009
Order Number: 320066-003US