EP80579 Datasheet, PDF (1482/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4.8
RDT – Receive Descriptor Tail Register
This register contains the tail pointers for the receive descriptor buffer. The register
points to a 16B datum. Software writes the tail register to add receive descriptors to
the hardware free list for the ring.
Table 37-57. RDT: Receive Descriptor Tail Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 2818h
Offset End: 281Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 2818h
Offset End: 281Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 2818h
Offset End: 281Bh
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 16
15 : 00
Rsvd
RDT
Reserved
Receive Descriptor Tail
Sticky
Bit Reset
Value
0h
0h
Bit Access
RV
RW
37.6.4.9
RDTR – RX Interrupt Delay Timer (Packet Timer) Register
This register is used to delay interrupt notification for the receive descriptor ring by
coalescing interrupts for multiple received packets. Delaying interrupt notification helps
maximize the number of receive packets serviced by a single interrupt.
This feature operates by initiating a countdown timer upon successfully receiving each
packet to system memory. If a subsequent packet is received BEFORE the timer
expires, the timer is reinitialized to the programmed value and re-starts its countdown.
If the timer expires due to NOT having received a subsequent packet within the
programmed interval, pending receive descriptor writebacks are flushed and a receive
timer interrupt is generated.
Setting the value to 0b represents no delay from a receive packet to the interrupt
notification, an results in immediate interrupt notification for each received packet.
Writing this register with FPD set initiates an immediate expiration of the timer, causing
a writeback of any consumed receive descriptors pending writeback, and results in a
receive timer interrupt in the ICR.
Receive interrupts due to a Receive Absolute Timer (RADV) expiration cancels a
pending RDTR interrupt. The RDTR countdown timer is reloaded but halted, so as to
avoid generation of a spurious second interrupt after the RADV has been noted, but
might be restarted by a subsequent received packet.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1482
August 2009
Order Number: 320066-003US