EP80579 Datasheet, PDF (701/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 17-19. Offset 3000h: TCTL - TCO Control Register (Sheet 2 of 2)
Description:
View: IA F
Base Address: RCBA
Offset Start: 3000h
Offset End: 3001h
Size: 8 bit
Default: 0h
Power Well: Core
Bit Range
06 : 03
02 : 00
Bit Acronym
Bit Description
Sticky
Reserved
IS
Reserved
TCO IRQ Select: Specifies on which IRQ the TCO
internally appears. If not using the APIC, the TCO
interrupt must be routed to IRQ9-11, and that interrupt is
not sharable with the SERIRQ stream, but it can be shared
with other PCI interrupts. If using the APIC, the TCO
interrupt can also be mapped to IRQ20-23 and can be
shared with other interrupt.
Bits SCI Map
000 IRQ9
001 IRQ10
010 IRQ11
011 Reserved
100 IRQ20 (only if APIC enabled)
101 IRQ21 (only if APIC enabled)
110 IRQ22 (only if APIC enabled)
111 IRQ23 (only if APIC enabled)
When setting these bits, the IE bit must be cleared to
prevent glitches.
When the interrupt is mapped to APIC interrupts 9, 10, or
11, the APIC must be programmed for active-high
reception. When the interrupt is mapped to APIC
interrupts 20 through 23, the APIC must be programmed
for active-low reception.
Bit Reset
Value
0h
000h
Bit Access
RW
17.1.5
17.1.5.1
Interrupt Configuration Registers
Offset 3100h: D31IP - Device 31 Interrupt Pin Register
Table 17-20. Offset 3100h: D31IP - Device 31 Interrupt Pin Register
Description:
View: IA F
Base Address: RCBA
Offset Start: 3100h
Offset End: 3103h
Size: 32 bit
Default: 00042210h
Power Well: Core
Bit Range
31 : 16
15 : 12
11 : 08
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
SMIP
SIP
Reserved
PIP
Reserved
SM Bus Pin: See the CIP description. This field applies to
the SM Bus controller.
SATA Pin: See the CIP description. This field applies to
the SATA controller.
Reserved
PCI Bridge Pin: See the CIP description. This field
applies to the PCI bridge. Currently, the PCI bridge does
not generate an interrupt so this field is read-only and ‘0’.
Bit Reset
Value
0h
2h
2h
1h
0h
Bit Access
RW
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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