EP80579 Datasheet, PDF (1108/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 29-4. Offset 0Ah: RTC_REGA - Register A (General Configuration) (Sheet 2 of 2)
Description:
View: IA F
Base Address: RTC Standard RAM Bank
Offset Start: 0Ah
Offset End: 0Ah
Size: 8 bit
Default: XXh
Power Well: RTC
Bit Range
06 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Division Chain Select: These three bits control the
divider chain for the oscillator, and are not affected by
RSMRST# or any other reset signal. DV[2] corresponds to
bit 6.
DV
DV2 DV1 DV0 Function
0
1
0
Normal Operation
1
1
X
Divider Reset
0
0
1
Invalid
0
0
0
Invalid
Rate Select: Selects one of 13 taps of the 15 stage
divider chain. The selected tap can generate a periodic
interrupt if the PIE bit is set in Register B. Otherwise this
tap sets the PF flag of Register C. If the periodic interrupt
is not to be used, these bits should all be set to zero. RS3
corresponds to bit 3.
RS3 RS2 RS1 RS0 Periodic Rate
0
0
0
0
Interrupt never toggles
0
0
0
1
3.90625 ms
0
0
1
0
7.8125 ms
0
0
1
1
122.070 ms
0
1
0
0
244.141 ms
RS
0
1
0
1
488.281 ms
0
1
1
0
976.5625ms
0
1
1
1
1.953125 ms
1
0
0
0
3.90625 ms
1
0
0
1
7.8125 ms
1
0
1
0
15.625 ms
1
0
1
1
31.25 ms
1
1
0
0
62.5 ms
1
1
0
1
125 ms
1
1
1
0
250 ms
1
1
1
1
500 ms
Bit Reset
Value
X
X
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1108
August 2009
Order Number: 320066-003US