EP80579 Datasheet, PDF (150/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
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Table 5-12. Summary of SMBus Interface Error Conditions
Event
Device Error
Bus Error
Failed Bus
Transaction
Parity Error
System Error
Type
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Fatality^a
Fatal
Fatal
Fatal
Fatal
Fatal
Reports via
Interrupt, SMI^b Device error.
Interrupt, SMI^b Bus error.
Notes
Interrupt, SMI^b Bus transaction failed.
SERR
SERR
Parity error detected.
System error detected.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
b. Based on HCFG register values.
Table 5-13 summarizes the capabilities of the SMBus controller error handling for each
of the features that the unit is expected to provide.
Table 5-13. Summary of SMBus Controller Error Reporting Capabilities
Feature
Enabling and Masking Error
Reporting
Logging Details
Reporting Multiple Errors
Data Poisoning
Implementation
The CMD and USBINTR registers enables and masks error reporting.
The USB 1.1 interface captures the type of event detected in the DSR,
HSTS, and AUXS registers.
The SMBus interface does not capture multiple events.
IICH backbone does not support data poisoning.
For additional details on error handling in the SMBus controller, see Section 24.0,
“SMBus Controller Functional Description: Bus 0, Device 31, Function 3”.
5.4.2
LPC Interface
The IICH provides a LPC interface that uses the PCI SERR infrastructure to report
errors. Table 5-14 summarizes the error conditions that the controller reports.
.
Table 5-14. Summary of LPC Interface Error Conditions
Event
Type
Fatality^a
Reports via
Notes
Parity Error
System Error
Uncorrectable
Uncorrectable
Fatal
Fatal
SERR
SERR
Parity error detected.
System error detected.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-15 summarizes the capabilities of the LPC interface error handling for each of
the features that the unit is expected to provide.
Table 5-15. Summary of LPC Interface Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Implementation
The CMD register supports error enabling and masking.
Intel^® EP80579 Integrated Processor Product Line Datasheet
150
August 2009
Order Number: 320066-003US