EP80579 Datasheet, PDF (839/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.5.1
C0
C0
C4
C4
D0
D3
E0
E3
E4
E7
E8
EB
F8
FB
ATC
ATS
SP
BFCS
BFTD1
BFTD2
MANID
APM Trapping Control
APM Trapping Status
Scratch Pad
BIST FIS Control/Status
BIST FIS Transmit Data, DW1
BIST FIS Transmit Data, DW2
Manufacturer’s ID
Offset 90h: MAP – Port Mapping Register
Table 23-32. Offset 90h: MAP – Port Mapping Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 90h
Offset End: 90h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 06
05 : 02
Bit Acronym
Bit Description
Sticky
SMS
Reserved
SATA Mode Select (SMS): SW programs these bits to
control the mode in which the SATA HBA should operate:
00b = IDE mode
01b = AHCI mode
10b = Reserved
11b = Reserved
Notes:
• IDE mode can be selected when AHCI is enabled.
• "Programming these bits with values that are illegal
will result in indeterministic behavior by the HW.
—
Reserved
Map Value (MV): The value in the bits below indicate the
address range the SATA ports responds to.
Bit Reset
Value
00h
0h
Bit Access
RW
RO
01 : 00
Primary
Bits Mode
Master
Secondary
Master
MV
00
Non-
combined
Port 0
Port 1
01 Reserved
10 Reserved
11
Reserved
00h
RO
23.1.5.2
Offset 92h: PCS – Port Control and Status Register
This register is only used in systems that do not support AHCI. In AHCI enabled
systems, bits[3:0] must always be set, and the status of the port is controlled through
AHCI memory space.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
839