EP80579 Datasheet, PDF (121/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
3.7.2
In this figure, PCI bus 0 originates in the IMCH and reaches internal IMCH PCI devices
through internal paths. Bus 0 is bridged into the IICH via an NSI interconnect and into
the AIOC. The memory controller materializes internally to the IMCH as device 0 of PCI
bus 0. The internal transparent bridge materializes the devices for the AIOC through a
bridged hierarchy as Figure 3-4 illustrates. In this hierarchy, a Transparent PCI-to-PCI
bridge appear on PCI bus 0 with the remaining AIOC devices materializing behind the
bridge on PCI bus M¹.
Device Tree
This section describes how the devices on the EP80579 die map onto the PCI device
tree. In general, the EP80579 exposes the structures and sub-blocks that Section 3.7.1
describes through PCI devices that materialize behind a transparent bridge on bus 0.
Figure 3-4 presents an overview of the device tree for on-die EP80579 software-visible
sub-blocks (see also Figure 13-1, “Bus 0 Device Map” on page 348).
Figure 3-4. Overview of PCI infrastructure for On-die Devices
PCI Bus 0
PCI Bus 0
Transparent
PCI-to-PCI
Bridge
PCI Bus M
As mentioned earlier, AIOC devices materialize on bus “M” behind a bridge on PCI bus 0
where the IA BIOS or O/S assign the secondary bus number “M” at discovery.
Devices can request space in the system memory and I/O address maps through BARs
in the configuration header. In general, the EP80579 materializes most device control
and status registers in memory-mapped regions allocated by a BAR. The only exception
1. The IA BIOS and/or O/S assigns the specific bus number during PCI discovery and enumeration.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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